Senior Staff SoC Design Engineer

Marvell Technology•Santa Clara, CA

2d•$134,390 - $201,300

About The Position

The Senior Staff SoC Design Engineer role focuses on SoC microarchitecture, RTL design, and full-chip integration for high-performance designs. The position involves implementing and integrating complex IP across subsystems, ensuring correct functionality while meeting performance, power, and area (PPA) targets at the SoC level. Responsibilities span the full front-end design flow — from architecture and specification through RTL development, integration, and design sign-off — in close collaboration with verification, physical design, and architecture teams.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
Proven experience delivering complex SoCs to tape-out and working across subsystem boundaries.
Strong RTL design skills in SystemVerilog and hands-on experience with SoC integration and debug.
Familiarity with AMBA protocols (AXI) and SoC interconnect architectures, along with clock/reset design, CDC, and timing constraints.
Understanding of how RTL decisions impact physical implementation.
Experience with scripting (Python or Tcl) for automation.

Nice To Haves

Exposure to emerging interconnect standards such as UCIe and UALink is preferred.

Responsibilities

Define microarchitecture and develop SystemVerilog RTL for SoC-level components, including interconnects, memory interfaces, and global logic such as reset, clocking, and power management.
Integrate processor clusters, memory controllers (HBM/DDR), and high-speed interfaces with a focus on interface definition, data flow, and system-level behavior.
Collaborate with verification teams to review test plans, support functional debug, and help close coverage gaps during development.
Run standard design checks such as lint and CDC/RDC, define timing constraints, and work with synthesis and physical design teams to ensure the design meets implementation requirements.
Coordinate with IP, SerDes, and analog teams to integrate complex interfaces and resolve subsystem-level issues.
Contribute to design methodology, improve integration workflows, and provide technical guidance to other engineers.