Senior Staff Engineer, Design Verification

Marvell Technology•Westborough, MA

19h•$151,000 - $223,440

About The Position

As part of the Design Verification Team at Marvell, you will verify complex semiconductor solutions across networking, compute, storage, and infrastructure domains. These designs enable high-speed, low-latency, and power-efficient data movement for data centers, telecom and enterprise networking, including both standard and customer-specific silicon. You will ensure designs meet stringent functional and performance requirements while contributing to next-generation AI and accelerated computing architectures. This includes supporting re-architecture efforts for AI-driven workloads, validating system-level performance, and helping identify and resolve architectural bottlenecks in scalable, high-bandwidth, and energy-efficient platforms. In this role, you will lead the verification of complex SoC and IP designs across high-performance computing, networking, and infrastructure domains by defining verification strategy, developing test plans, and driving closure using advanced UVM methodologies, including constrained-random testing, functional coverage, and assertions. You will own RTL simulation and debug activities, perform root-cause analysis of complex issues, and work closely with design and architecture teams to ensure correctness and scalability. You will also lead execution across projects by managing milestones and deliverables, while mentoring junior engineers, promoting verification best practices, and contributing to improvements in automation, regression efficiency, and overall verification infrastructure, with the ability to influence key design and architectural decisions.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or a related field, with 5–10 years of relevant professional experience. Or Master’s degree and/or PhD in Computer Science, Electrical Engineering, or a related field, with 3-5 years of professional experience required.
Strong expertise in digital design fundamentals, including finite state machines (FSMs), combinational and sequential logic, and computer architecture, with understanding of industry protocols such as AMBA, PCIe, Ethernet, and memory coherency architectures, applied in verification environments.
Solid experience with hardware verification methodologies, including UVM (Universal Verification Methodology), constrained-random verification, functional coverage analysis, and assertion-based verification (SVA), with ability to apply them in block-level and subsystem verification.
Strong software and automation skills, including C/C++ development and scripting using Python, Perl, or similar languages, with experience in Linux-based development environments and command-line tools for verification and debugging workflows.
Deep knowledge of SoC/ASIC design and verification flows, including RTL simulation, debugging, and root-cause analysis, with ability to independently resolve complex technical issues and deliver high-quality verification results.
Strong collaboration skills with experience working across cross-functional teams, including design and architecture, along with ability to communicate clearly, document effectively, and contribute to design and verification reviews.
Proven ability to mentor junior engineers, provide technical guidance, and promote best practices in verification methodology, reuse, and code quality.
Proven experience leading verification projects and managing execution across teams, including planning, task distribution, tracking deliverables, managing dependencies, and driving verification milestones to closure in complex projects.
Demonstrated technical leadership in driving verification strategy, influencing architecture and design decisions, and ensuring verification completeness and sign-off for complex IP and SoC systems.

Responsibilities

Serve as an expert in driving the architecture and development of scalable UVM-based verification environments for complex IP and SoC designs, including defining reusable frameworks, infrastructure strategy, and long-term scalability.
Define the scope for DV, emulation, and post-silicon validation, and collaborate with stakeholders to establish timelines and ensure execution.
Lead execution across projects by managing milestones and deliverables, while mentoring junior engineers, promoting verification best practices, and contributing to improvements in automation, regression efficiency, and overall verification infrastructure, with the ability to influence key design and architectural decisions.
Lead deep RTL and system-level debug efforts, performing complex root-cause analysis across design, testbench, and integration layers, and driving cross-functional resolution of critical issues impacting quality and schedules.
Provide technical leadership across verification efforts by driving design and verification reviews, defining methodology standards, and influencing design-for-verification decisions at the architecture level.
Lead and coordinate cross-functional execution across verification teams and stakeholders, managing risks, dependencies, and schedules while communicating status, trade-offs, and technical decisions to ensure alignment and closure.
Apply formal verification techniques, including writing SystemVerilog Assertions (SVA) and defining formal properties, using formal tools for property and equivalence checking, and collaborating with design teams to identify corner cases, debug issues, and complement simulation-based verification.