Staff Engineer, Design Verification

Marvell Technology•Santa Clara, CA

21h•$113,920 - $170,600

About The Position

As a SoC-level design verification engineer, you will be responsible for the development and maintenance of UVM testbench components and other verification testing collaterals. You will be a member of a team charged with ensuring design quality in a variety of complex SoC architectures. Analyze architectures and designs to create comprehensive test plans and strategies. Contribute to the development of verification environments. Develop tests/testing strategies to achieve coverage goals. Debug failures and work with designers to resolve issues.

Requirements

Bachelor’s degree in Computer Engineering, Electrical Engineering or related fields and 3+ years of related professional experience. Or Master’s degree and/or PhD in Computer Engineering, Electrical Engineering or related fields with 2+ years of experience.
Experience with System Verilog/UVM
Experience with writing and executing detailed verification test-plan.
Experience with verification tools, as well as bug tracking and regression mechanisms.
Excellent communication skills
Demonstrates good analytical and problem-solving skills.
Basic proficiency with C/C++.
Experience with scripting languages, e.g., Python or Perl
Working knowledge of the Linux operating system

Responsibilities

Development and maintenance of UVM testbench components and other verification testing collaterals.
Ensuring design quality in a variety of complex SoC architectures.
Analyzing architectures and designs to create comprehensive test plans and strategies.
Contributing to the development of verification environments.
Developing tests/testing strategies to achieve coverage goals.
Debugging failures and working with designers to resolve issues.