Staff Engineer, Design Verification

Marvell Technology•Westborough, MA

23h•$128,000 - $189,370

About The Position

As part of the Design Verification Team at Marvell, you will verify complex semiconductor solutions across networking, compute, storage, and infrastructure domains. These designs enable high-speed, low-latency, and power-efficient data movement for data centers, telecom and enterprise networking, including both standard and customer-specific silicon. You will ensure designs meet stringent functional and performance requirements while contributing to next-generation AI and accelerated computing architectures. This includes supporting re-architecture efforts for AI-driven workloads, validating system-level performance, and helping identify and resolve architectural bottlenecks in scalable, high-bandwidth, and energy-efficient platforms.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or a related field, with 3–5 years of relevant professional experience. Or Master’s degree and/or PhD in Computer Science, Electrical Engineering, or a related field, with 2-3 years of professional experience required.
Solid experience with hardware verification methodologies, including UVM (Universal Verification Methodology), constrained-random verification, functional coverage analysis, and assertion-based verification (SVA).
Strong foundation in digital logic design, finite state machines (FSMs), combinational and sequential circuit design, and computer architecture principles, with familiarity in industry-standard protocols such as AMBA, PCIe, Ethernet, and memory coherency architectures.
In-depth knowledge of SoC/ASIC design and verification flows, with proficiency in RTL simulation and debugging. Capable of resolving complex technical issues independently, exercising sound judgment, and successfully delivering projects with minimal supervision.
Collaborates closely with cross-functional teams and fosters productive working relationships. Possesses strong communication and documentation skills, with the ability to mentor and guide junior engineers by coaching and directing less experienced team members
Experience in C/C++ development, advanced scripting in Python, Perl, or similar languages for automation and tooling, and extensive hands-on experience in Linux environments and command-line utilities.

Responsibilities

Architect, develop, and maintain scalable UVM-based verification environments for complex IP and SoC designs, including reusable testbench components and infrastructure.
Define and drive verification strategy and planning, including test methodologies, coverage models, and sign-off criteria, while ensuring end-to-end verification closure.
Develop and execute advanced constrained-random and directed verification testbenches, perform coverage analysis, and ensure comprehensive functional verification against design specifications.
Perform deep RTL debugging and root-cause analysis of complex functional and system-level issues, working closely with design and architecture teams to ensure high-quality, testable implementations.
Lead verification efforts by conducting design and verification reviews, mentoring junior engineers, and improving automation and regression infrastructure to enhance efficiency and quality.
Communicate effectively with cross-functional teams and stakeholders to present verification status, highlight risks, and drive technical discussions to resolution.