Senior Speed Characterization Engineer - Silicon Co-Design Group

NVIDIA•Us, CA

10d•Hybrid

About The Position

NVIDIA silicon runs the world's AI infrastructure. The frequency it delivers across every voltage, process corner, and workload is not assumed. It is measured, correlated, and validated. This role does that work. The Silicon Co-Design Group is where architecture intent becomes silicon reality. We own the boundary between what was designed and what was built, and we are the team that knows the difference. When a program ships at frequency and at quality, this team is a reason why. You will be the person who follows through between simulation and silicon. When the model is wrong, a frequency corner that doesn't hold, a Vmin that walks, a critical path that timing analysis missed, you find out why, and your data is what the rest of the program acts on. Architecture, design, and product teams do not guess. They use your numbers. The engineers who do this well are rare. They think like circuit designers, work like experimentalists, and reason like data scientists. If that is you, read on.

Requirements

BS or MS in Electrical Engineering, Computer Engineering, or Systems Engineering, or equivalent experience.
5+ years with hands-on silicon: bring-up, post-silicon speed validation, frequency characterization, or timing analysis on real hardware.
Strong computer architecture fundamentals including pipeline structures, clocking, memory hierarchies, and how microarchitectural decisions propagate into frequency and power.
Depth in static timing analysis, critical path identification, and the ability to read and reason about timing reports at the block and chip level.
Enough design intuition to know what you're measuring and enough statistical fluency to know what the data means.
Proficiency in silicon margining, guard-banding, and PVT/binning dependencies.
Scripting depth in Python, Perl, or C/C++.
You build the tools your work depends on.

Nice To Haves

You've closed the prediction-to-silicon loop with a correlation methodology precise enough that other teams adopted it.
You've traced a frequency miss to a specific critical path, microarchitectural interaction, or process corner and driven the fix all the way through.
Built or deployed AI-driven flows for characterization or analysis, and can speak to both the outcome and the guardrails you put in place.
Background is in datacenter-scale or high-performance silicon and you know how complexity at scale changes the failure landscape and raises the cost of being wrong.

Responsibilities

Own silicon speed characterization from first power-on through production sign-off, covering frequency, Vmin, Vmax, and timing margins across the full PVT space.
Close the correlation gap. Tie pre-silicon timing analysis and critical path predictions to measured silicon, quantify where the model diverges from reality, and produce analysis that architecture and design can act on with confidence.
Trace failures to their source, whether a microarchitectural bottleneck, a critical path that doesn't close under voltage, a clocking issue, or a process corner the model didn't anticipate, and drive the resolution.
Own and build AI agents that work at your direction: automated test orchestration, intelligent data pipelines, and analysis flows that expand coverage and compress cycle time without sacrificing difficulty.
Know where AI accelerates real work and where it introduces risk.
Sit at the decision table. Your data surfaces tradeoffs across architecture, VLSI, ASIC, firmware, and product teams. Your analysis is what settles calls.