Principal Chip Lead, Silicon Co-Design Group

NVIDIA•Us, CA

10d•Hybrid

About The Position

The Silicon Co-Design Group (SCG) operates at the intersection of architecture, design, marketing, operations, and productization, covering the entire lifecycle from early architecture to final product delivery across various markets including Datacenter, Gaming, Robotics, Automotive, and Embedded. We are seeking a Chip Lead to be the technical leader for a significant silicon program within NVIDIA's Silicon Co-Design Group. This role is distinct from project management or a senior IC position. The Chip Lead will be the primary technical point of contact for complex technical challenges, providing a unified technical perspective for leadership decisions. This role is accountable for the end-to-end technical integrity of the chip, guiding feature integration, resolving critical multi-functional bugs, and managing the qualification process.

Requirements

BS or MS (or equivalent experience) in Electrical or Computer Engineering.
Over a decade of proven track record in post-silicon bring-up, validation, or system integration leadership at a major semiconductor company.
Experience with multiple shipped silicon products.
15+ years of experience.
Strong end-to-end understanding of SoC and ASIC architecture.
Recognized expertise in at least one subsystem such as HBM, SerDes, power and thermal, or packaging.
Specific examples of silicon-level impact (e.g., faster bring-up, fewer escapes, yield recovery, methodology contributions).
Experience turning ambiguous, multi-team failure modes into root-cause closure with reusable workarounds and write-ups.
Track record of guiding technical decisions across functional boundaries without direct reporting authority.
Ability to translate sophisticated silicon issues into clear options for executive audiences.

Nice To Haves

Prior experience as a Chip Lead, Project Tech Lead, or Principal or Distinguished Engineer on a flagship GPU, AI accelerator, CPU, networking ASIC, or other large SoC.
Patents, conference papers, invited talks, or recognized contributions to silicon validation, post-silicon debug, or co-design integration.
History of building and sharing technical methodology beyond a single program (reusable playbooks, debug frameworks, or standards adopted by other teams).
Hands-on debug experience with HBM, high-speed I/O, power and thermal, or packaging.
Comfort working through ambiguity with globally distributed teams.
Habit of surfacing the right risks and recommendations to leadership without being asked.
Experience using AI tools to lift team velocity.

Responsibilities

Serve as the single technical point of contact for multi-functional decisions, issues, and trade-offs.
Co-lead program-level feature integration from chip to system, identifying and resolving inter-function dependencies.
Resolve complex multi-functional bugs by translating ambiguous symptoms into root-cause closure in areas such as HBM, power and thermal, high-speed I/O, and packaging.
Steward the qualification playbook, guiding mitigations for non-standard situations and capturing lessons learned for methodology improvement.
Shape the program’s technical narrative by presenting key risks, trade-offs, and mitigations as decision-ready options for executive leadership.
Mentor other Chip Leads on adjacent silicon programs and contribute to SCG-wide methodology through post-mortems and documentation.
Lead the program’s Critical Debug and SCG Technical Execution forums.
Represent the chip externally, providing early insight into technical risks.