Senior Signal Integrity Engineer
Qualcomm•San Diego, CA
•$127,200 - $190,800
About The Position
This role represents an individual contributor within the CHS Signal Integrity organization responsible for end-to-end signal integrity and power integrity architecture, analysis, and signoff for next-generation mobile, compute, automotive, and various other connectivity platforms. The engineer acts as System SI/PI owner across full platform (SoC ↔ package ↔ board ↔ connectors ↔ external systems), Technical owner for high-speed interfaces and system margins, and Cross-functional leader driving SIPI driven design convergence across silicon, package, and platform teams.
Requirements
- 4+ years’ experience in Signal Integrity / Power Integrity / High-speed systems
- Expertise in Transmission line theory, EM fundamentals, SI/PI interactions, and jitter/noise coupling.
- Hands-on experience with: Tools such as HFSS, ADS, Sigrity, CST, SIwave, HSPICE; and measurement instruments such as VNA, TDR, real-time scopes
- Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 2+ years of System/Package Design/Technology Engineering or related work experience.
- OR Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 1+ year of System/Package Design/Technology Engineering or related work experience.
- OR PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field.
Responsibilities
- Own end-to-end SI/PI closure for programs (pre-silicon → post-silicon → production)
- Define design targets and layout design guidelines for all high-speed interfaces
- Influence architecture decisions early in product lifecycle
- Ensure SI/PI alignment with product KPIs (performance, yield, power, cost)
- Ensure compliance to standards (JEDEC, PCI-SIG, MIPI, IEEE)
- Influence PDN architecture definition at system and package level, provide related optimum cost solutions
- Ensure cross functional alignments. Partner with SoC/PHY design teams, Package engineering, Board/system teams, and OEM/ODM ecosystem
- Lead design reviews and signoff decisions
- Represent SI/PI in program reviews and leadership forums
- Drive correlation between pre-silicon models and silicon/lab data
- Lead debug of eye collapse / jitter margin issues, crosstalk and power noise and silicon-package-board interactions
- Drive adoption of best practices across programs
- Drive improvements in methods for system SI/PI
- Drive SI/PI for interfaces such as: Memory: LPDDR4/5/6; High-speed IO: PCIe Gen4/5/6/7, USB4, UFS, 10G–112G+ PHYs; Camera/Display: MIPI CSI/DSI; System PDN
Benefits
- competitive annual discretionary bonus program
- opportunity for annual RSU grants
- highly competitive benefits package
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What This Job Offers
Job Type
Full-time
Career Level
Senior
