Senior Signal Integrity Engineer

Broadcom•San Jose, CA

1d•$143,800 - $230,000

About The Position

We are looking for a Senior SI/PI Engineer to join our hardware engineering team. In this role, you’ll own the signal and power integrity analysis for our high-speed boards, packages, and system architectures. You will work directly with hardware, ASIC, SERDES, packaging, and layout engineers from early architecture trade-offs all the way through lab bring-up and characterization. If you enjoy building accurate 3D simulation models, developing optimized solutions, and validating designs in lab, this role is for you.

Requirements

BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
12+ years of practical experience in high-speed digital design, signal integrity, and power integrity.
Solid understanding of transmission line theory, S-parameters, crosstalk, jitter, EMI/EMC, and PDN concepts.
Hands-on proficiency with tools like Ansys HFSS/SiWave, Cadence Sigrity/Allegro, Keysight ADS, or HSPICE.
Direct experience simulating and analyzing high-speed interfaces (e.g., PCIe, 56G/112G/224G SerDes, DDR4/5, or HBM).
Comfortable operating high-frequency test equipment (VNAs, TDRs, high-bandwidth scopes), probing techniques, and performing model-to-hardware correlation.

Nice To Haves

Familiarity with high-speed PCB laminates, stackups, via designs, and manufacturing trade-offs.
Experience writing Python or TCL scripts to automate EDA tools.

Responsibilities

Build 2.5D/3D EM models for high-speed channels, package substrates, connectors, and PCB stackups.
Perform time- and frequency-domain simulations for high-speed serial links (SerDes) and parallel interfaces (DDR/HBM).
Assist in AC/DC power delivery network simulations to evaluate impedance targets, transient noise, and IR drop across boards and packages.
Provide clear layout constraints, stackup recommendations, and routing rules to hardware and layout teams.
Optimize custom package designs, connector breakouts, and practical via designs.
Iterate as bottlenecks are discovered.
Validate simulations in the lab using VNAs, TDRs, BERTs, and real-time oscilloscopes.
Correlate measurement data back to your models to refine future design rules.
Partner with hardware teams during board bring-up to debug SI/PI issues and root-cause signal degradation or power noise.
Leverage scripts (Python, TCL) to automate simulation flows, data processing, and design checks.