Senior RTL Design Engineer

Advanced Micro Devices, IncMarkham, ON
Hybrid

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. ASIC Design Engineer with hands-on experience across all aspects of IP RTL design, including architecture development, RTL implementation, verification support, and silicon bring-up. Proven expertise in leveraging and deploying AI-generated RTL solutions in production silicon, driving improved design productivity, quality, and time-to-market while ensuring robust functionality and performance.

Requirements

  • Strong working experience in RTL coding using Verilog HDL
  • Strong experience with integrating AI-assisted design methodologies into advanced semiconductor development flows from concept through tapeout and post-silicon validation.
  • Experience in design with multiple clock domains
  • Experience in using lint and CDC tools
  • Experience in developing specification
  • Understanding of high-speed I/O protocols (PCIe, USB, SATA, Ethernet…)
  • Bachelors or Masters degree in Computer Engineering/ Electrical Engineering

Responsibilities

  • IP RTL design for AMDs PCI Express (PCIe) IP used for all next generation server, clients, GPU and Semi-custom products.
  • Work closely with IP and system architects to micro-architect cutting edge features.
  • Apply low power design techniques to existing logic and maintain overall system performance.
  • Focus on timing, LINT and CDC closure to ensure high quality RTL.
  • Support verification and debug of the ASIC throughout various stages of the project.

Benefits

  • AMD benefits at a glance.
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