RTL Design Engineer

Advanced Micro Devices, Inc•Markham, ON

2d•Hybrid

About The Position

As a member of AMD's PCIe Subsystem (PCIeSS) organization, you will join the PCIe IP Enablement (IPE) team as a senior RTL design engineer. You will work closely with the architecture, IP design, physical design, verification, and DFx teams to design and deliver high-quality PCIe subsystem RTL and achieve first-pass silicon success.

Requirements

RTL design experience
Proven end-to-end ownership of complex digital IP/subsystems from architecture through tape-out
Highly accurate and detail-oriented
Strong communication and problem-solving skills
Experience with Verilog / SystemVerilog RTL design
VCS simulation
Perl/Shell scripting
Familiarity with subsystem integration (tile flow, repeaters, SRAM generation, ECO)
DFx awareness (DFT / DFD)
Excellent problem-solving and debugging skills
Bachelor's or Master's degree in Electrical Engineering / Computer Engineering

Nice To Haves

Strong RTL design and micro-architecture experience on complex digital IP/subsystems, from RTL to tape-out
Strong AI knowledge and experience in its usage to develop skills and agents
Direct PCIe protocol and subsystem design experience
Proficiency with RTL quality flows: Lint, CDC/RDC, synthesis, LEC, and STA

Responsibilities

Micro-architecture and RTL design for PCIe subsystem blocks
Develop and maintain RTL for complex digital blocks; author and enforce RTL coding guidelines and design documentation
Translate architecture requirements into robust, reusable, high-quality RTL
Drive design reviews and resolve complex RTL debug and correctness issues
Support subsystem integration and SoC delivery
Ensure RTL closes cleanly through front-end signoff — Lint, CDC/RDC, synthesis, LEC, STA
Collaborate with verification, physical design, and architecture teams for seamless design handoff and sign-off