Senior RTL Design Engineer

Saige Partners • Folsom, CA

3d

About The Position

We strive to be Your Future , Your Solution to accelerate your career! Contact Hannah Wilson at [email protected], you can also schedule an appointment at to learn more about this opportunity! Position: Senior RTL Design Engineer (Folsom, CA) Job Overview: We are seeking an experienced Senior RTL Design Engineer to lead the design and implementation of advanced FPGA-based solutions. This role will focus on architecture development, high-speed interface design, and RTL implementation for complex systems. The ideal candidate will collaborate with cross-functional teams to drive designs from architectural concept through FPGA validation and silicon verification while optimizing performance, power, and area. This is a contract role and is not eligible for C2C or W2 referral candidates. What you will be doing as a Senior RTL Design Engineer…

Requirements

• Bachelor’s degree in Computer Engineering, Electrical Engineering, or Computer Science (Master’s or PhD preferred).
• 10+ years of experience in architecture development and FPGA design.
• Strong experience with FPGA HDL development, simulation, and analysis.
• Proficiency in VHDL and/or Verilog for RTL design.
• Experience performing static timing analysis and timing closure for high-performance FPGA designs.
• Experience with RoCEv2 (RDMA over Converged Ethernet) including: o RDMA READ/WRITE operations o Queue Pair (QP) management o Congestion control
• Experience developing NVMe over Fabrics RTL, enabling direct data transfer between host memory and storage targets.
• Experience tuning and integrating high-speed interfaces, including: o PCIe Gen4/5/6 o 100G / 200G / 400G Ethernet MAC/PCS
• Demonstrated ability to work effectively in a collaborative engineering environment.

Responsibilities

• Participate in defining system architecture and microarchitecture for complex FPGA-based designs.
• Develop prototypes, simulate models, and define system-level requirements and specifications.
• Architect and implement multi-FPGA partitioning solutions for scalable hardware systems.
• Design, implement, and debug high-speed interfaces, including Ethernet, PCIe, and DDR.
• Apply RTL design and implementation techniques to meet power, performance, and area (PPA) goals in collaboration with physical implementation teams.
• Develop and release FPGA designs through the full development lifecycle including: o Microarchitecture definition o RTL design and implementation o Physical implementation o Timing closure o Simulation and validation o Lab-based silicon validation
• Perform design trade-off analysis to optimize cost, size, power consumption, performance, and feature sets.
• Collaborate with cross-functional teams including architecture, verification, and hardware validation groups.

What This Job Offers

• Career Level: Mid Level