Senior Product Development Engineer

NVIDIA•Santa Clara, CA
•$168,000 - $322,000

About The Position

NVIDIA is seeking experienced Product Development Engineers to join its Operations Product Development Engineering GPU Team. The team productizes NVIDIA chips for consumer, professional, and datacenter markets. In this role, you will help bring the latest architecture designs to market by developing final-test processes for advanced GPUs, improving manufacturing efficiency, identifying yield bottlenecks, and resolving test failures at wafer and package levels. You will collaborate across engineering and operations functions to investigate technical problems and contribute to future ASIC designs that improve test coverage, product yield, test time, silicon bring-up, and releases.

Requirements

  • Master's degree in Electrical Engineering or equivalent experience.
  • Eight or more years of product development engineering or relevant experience.
  • Attention to detail, strong problem-solving skills, data-driven decision-making, critical thinking, and a solution-focused approach.
  • Experience with digital design, circuit analysis, characterization, and qualification.
  • Knowledge of ATE test flows, DFT, and device physics.
  • Proficiency in statistical data analysis using JMP or other tools.
  • Strong interpersonal communication and cross-functional collaboration skills.
  • Ability to define problems and independently drive them to closure with minimal supervision.

Nice To Haves

  • Hands-on experience with an Advantest 93K tester using SMT7 or SMT8 OS.
  • Knowledge of test-time and DPPM reduction.
  • Experience with logic or SRAM and voltage/frequency characterization.
  • A DFT (design for test) background and familiarity with ATE test principles.
  • Examples of creative solutions to silicon or package problems.
  • Scripting or programming knowledge, such as Python or Perl.

Responsibilities

  • Design final-test (FT) processes to enhance manufacturing efficiency for the latest GPUs built using leading-edge process technology.
  • Identify and resolve yield bottlenecks, and analyze and drive resolution of test, wafer-level, and package-level failures on Automatic Test Equipment (ATE).
  • Propose design of experiments (DOEs) and develop solutions to complex characterization problems.
  • Lead cross-functional efforts with design, foundry, DFT, test, planning, and quality teams to identify root causes and solve technical problems.
  • Influence future ASIC designs to improve test coverage, product yield, test time, silicon bring-up, and releases.

Benefits

  • Equity
  • Benefits package
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