Eng Sr Prin - Elec

BAE Systems•Cedar Rapids, IA
•$145,049 - $246,584•Onsite

About The Position

BAE Systems is seeking a Senior Principal FPGA Design Engineer to support FPGA designs through all phases of development. The ideal candidate will perform activities including assisting in requirements generation and design architecture, ownership of RTL coding, synthesis, place and route, timing closure, basic test bench development, lab testing and debug, and product support. This role requires full-time on-site performance due to the need for consistent, in-person collaboration and/or the requirement to perform all work onsite. A minimum of Secret Clearance is required, pursuant to a government contract.

Requirements

  • 8+ years of relevant experience with bachelor's degree (less years with advanced degree)
  • Current Security Clearance (Secret), or eligible to obtain one
  • Significant experience in FPGA (preferred) or ASIC Design / Development
  • VHDL (preferred) or Verilog HDL coding
  • Familiarity with Xilinx Vivado or Intel/Altera Quartus
  • Digital simulation using Modelsim/Questa
  • Significant experience with static timing analysis and clock domain crossing techniques
  • Experience with high speed interfaces like SERDES, PCIe, DDR2/3/4, LVDS
  • Familiarity with revision control (GIT, CVS, Clearcase, Subversion, etc.)
  • Some Experience generating scripts (Perl, Tcl, Python, shell, etc.)
  • Strong debug and problem solving skills
  • Strong written and oral communication skills
  • Self-starter and a good team player
  • Ability to mentor and willingness to be mentored

Nice To Haves

  • Ability to distill higher level requirements into micro-architecture
  • Experience modifying and enhancing legacy FPGA designs
  • Experience in leading a design team a plus
  • Experience in hardware design and hands-on lab debug
  • Experience working with FPGA design verification teams
  • Some experience with data conversion techniques (ADC/DAC) a plus

Responsibilities

  • Assisting in requirements generation and design architecture
  • Ownership of RTL coding
  • Synthesis, place and route
  • Timing closure
  • Basic test bench development
  • Lab testing and debug
  • Product support
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