Senior Principal Engineer

Renesas Electronics•San Jose, CA

12h•$239,000 - $299,000•Onsite

About The Position

Renesas is seeking a Power Design Engineer to lead development of test vehicles for high-current BCD and low-voltage GaN power process and product portfolios. The role owns test vehicle definition, circuit and layout design, and characterization planning from concept through silicon bring-up, in collaboration with process development, product engineering, and applications teams. The position calls for hands-on experience designing power devices and circuits at both IC and module level, along with knowledge of the power topologies the test vehicles are intended to support. The engineer will define and execute test vehicles, translate process and product requirements into architectures and specifications, design and simulate power stages, and characterize power devices. Work may extend to module and package co-design, evaluation boards, and system-level test vehicles. The role also includes developing test plans, supporting silicon bring-up and debug, correlating measurements with simulation and design targets, collaborating across engineering teams, and documenting results to inform technology qualification and product development. Renesas is an embedded semiconductor solution provider with a global team of more than 21,000 engineers and problem solvers in more than 30 countries. Its TAGIE culture emphasizes being Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas offers a competitive benefits package; further details will be provided during the hiring process. The company is an equal opportunity and affirmative action employer. The position may involve technology subject to U.S. export controls.

Requirements

Bachelor's or master's degree in Electrical Engineering, Microelectronics, or a related field.
At least 10 years of hands-on design experience in power semiconductor devices, analog/power ICs, or power electronics.
Strong working knowledge of power conversion topologies, including buck, boost, multiphase/interleaved converters, half-bridge, and DrMOS/Intelli-Phase-style architectures, and how topology choices drive device requirements.
Solid understanding of power device physics and tradeoffs across BCD process technologies and GaN, particularly low-voltage GaN HEMTs, including RDS(ON), switching loss, gate charge, breakdown/avalanche behavior, and thermal characteristics.
Demonstrated experience designing test structures or test chips/vehicles for process technology development, including defining what a process node needs to prove out.
IC-level design and layout experience, including parasitic-sensitive layout practices for high-current switching nodes.
Experience taking designs beyond the die level to module, package, or board level, such as power module co-design, evaluation board layout, or thermal/electrical co-design.
Proficiency with circuit simulation tools such as SPICE or equivalent, and familiarity with device/TCAD simulation concepts.
Ability to interpret and specify absolute maximum ratings, transient voltage tolerance, and protection thresholds (OVP/UVP/OCP/OTP) relevant to power-stage reliability.
Strong laboratory skills in bring-up, debug, and characterization using oscilloscopes, curve tracers, power analyzers, and thermal imaging.

Responsibilities

Define, design, and drive execution of test vehicles for high-current BCD and low-voltage GaN processes, including device test structures, scaled power stages, and full-function demonstration circuits.
Translate process capability targets and product roadmap requirements into test vehicle architectures and specifications.
Design and simulate power-stage circuits, such as synchronous buck/boost, multiphase, half-bridge/DrMOS, and gate-driver circuits, to validate device performance under realistic switching and thermal conditions.
Select and characterize power devices, including LDMOS, trench MOSFETs, low-voltage GaN HEMTs, and Schottky or synchronous rectifiers, in collaboration with device and process engineering.
Perform IC-level design and layout for test structures, using parasitic-aware practices for switch nodes, current sensing, and gate-drive paths.
Extend designs to the module or package level as needed, including co-design of power stages with packaging, magnetics, and PCB layouts for evaluation boards and system-level test vehicles.
Develop test and characterization plans for DC parametrics, switching performance, efficiency, transient response, and voltage/current stress margins, including switch-node ringing and absolute-maximum validation.
Lead or support silicon bring-up and debug, and correlate measured results with simulation and design targets.
Collaborate with process integration, reliability, product/applications engineering, and test engineering to connect process split data with product-ready specifications.
Document design methodology, test vehicle results, and characterization data to support technology qualification and product development decisions.