Senior Principal Engineer, Digital IC Design

Marvell Technology•Santa Clara, CA

1d•$158,600 - $237,600

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. As a Digital IC Design Principal Engineer with Marvell, you’ll be a member of the Central Engineering business group. Central Engineering provides IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a digital team of about eight people making a big impact on this organization, working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates. As a Principal Design Engineer, you will lead micro-architecture and RTL development and HW/SW co-design efforts working across multi-functional teams, in developing state-of-the-art designs for the up and coming CXL product roadmap.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience.
Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
Strong understanding of SoC architecture, processor cores, memory and peripheral interfaces through hands on prior experience.
Extensive experience in Verilog/VHDL, Spyglass and Quality checks of the implemented RTL for LINT, CDC.
Hands on experience in interpretive language such as Perl/Python.
Proven track record of delivering production-quality designs on aggressive development schedules.

Nice To Haves

Domain expertise in CXL/PCIe protocols, DDR memory controllers is a plus.

Responsibilities

Responsible for micro-architecture design and development of SOC and associated component IP like Memory Controllers/PCIE interface/CXL interfaces etc.
Working with Architects and Verification engineers to deliver develop complex, high performance and timing critical designs through all aspects of the SoC front-end design flow (incl. timing closure and power optimization)