Senior Principal Engineer, Digital IC Design
About The Position
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. The Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. This ASIC design engineer role is responsible for the design, verification, and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in engineering implementation spec writing from system requirements, RTL design, verification, synthesis, and static timing analysis. The responsibilities include improving the design methodology and flow, RTL designs for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications, collaborating with Analog/DSP/DV/FW/AE teams to deliver competitive SerDes IP solutions for all Marvell product lines, and providing support to product teams for both pre and post silicon.
Requirements
- MSEE with 10+ years of experience.
- Good personal communication skills and team working spirit.
- Hardworking and motivated to be part of a highly competent design team.
- Must be proficient in the following skills: Fundamental concepts in digital logic design
- Understand ASIC verification flows and methodologies
- Verilog and SystemVerilog/SystemC/Vera
- Strong Perl and Tcl scripting
- UNIX Shell scripting (Csh, Bash)
Nice To Haves
- Formal verification
- Low power design
- MATLAB and C/C++ based system simulation and evaluation
- DSP function hardware implementation knowledge
Responsibilities
- Improve the design methodology and flow.
- RTL designs for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications.
- Collaborate with Analog/DSP/DV/FW/AE teams to deliver the competitive SerDes IP solutions for all the Marvell product lines.
- Provide the support to the product teams, for both pre and post silicon.
Benefits
- employee stock purchase plan with a 2-year look back
- family support programs to help balance work and home life
- robust mental health resources to prioritize emotional well-being
- recognition and service awards to celebrate contributions and milestones
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What This Job Offers
Job Type
Full-time
Career Level
Senior
