Principal IC Digital Design - SoC Design/Micro-architecture

Marvell Technology • Santa Clara, CA

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About The Position

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Marvell Custom Solutions develops cutting-edge solutions for large AI, cloud data center, and telecom customers. The SoCs encompass best-in-class performance, advanced die-to-die and packaging technology, and optimized low-power techniques. The Principle Digital IC Design Engineer (DE06T5) is a senior individual contributor responsible for the design, integration, and delivery of complex digital logic for advanced SoC products. This role owns major IP blocks or subsystems and acts as a recognized technical authority within the program or department. Engineers at this level operate with minimal supervision and are accountable for design quality, schedule, and silicon readiness.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
• 12+ years of experience in digital IC or SoC RTL design
• Deep expertise in RTL using system verilog design and micro-architecture
• Strong understanding of clocking, reset, and power-aware design, SoC architecture, processor cores, memory, peripheral interfaces through hand on prior experience
• Hands-on experience with lint, CDC, and RDC analysis
• Proven ownership and track record of block or subsystem delivery on production silicon with aggressive development schedules.
• Strong debugging and problem-solving skills and multi-tasking
• Experience with ARM AMBA, PCIE, DDR, LPDDR, I2C/SMBus, I3C, USB, UART, QSPI/SPI
• Hands on experience in interpretive language such as Perl/Python.

Nice To Haves

• Experience with large-scale SoC integration
• Familiarity with low-power design techniques
• Exposure to synthesis, STA, or physical design flows
• Experience mentoring engineers or leading technical reviews

Responsibilities

• Own RTL design, implementation, and integration of complex blocks or subsystems
• Define and influence block-level and subsystem-level micro-architecture
• Develop high-quality, synthesizable RTL using Verilog/SystemVerilog
• Ensure design correctness through lint, CDC, RDC, and peer reviews
• Collaborate with verification, validation, Firmware and synthesis/STA, and physical design teams
• Identify and resolve complex functional, timing, power and integration issues
• Contribute to digital design methodologies and best practices
• Mentor and guide junior engineers
• Participate in design reviews and tape-out readiness

Benefits

• exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments.
• offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition.
• an employee stock purchase plan with a 2-year look back
• family support programs to help balance work and home life
• robust mental health resources to prioritize emotional well-being
• recognition and service awards to celebrate contributions and milestones.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Number of Employees: 1,001-5,000 employees