Senior Power Integrity Co-Design Engineer

NVIDIA•Santa Clara, CA

2d•$196,000 - $368,000•Hybrid

About The Position

Join NVIDIA, a trailblazer at the forefront of graphics and artificial intelligence performance, efficiency, and innovation. From our roots as a groundbreaking graphics company, we have evolved into a global leader in artificial intelligence, continuously pushing the boundaries to address sophisticated challenges across diverse industries. The Silicon Codesign Group (SCG) sits at the intersection of architecture, silicon, systems, and manufacturing- where deep engineering judgment drives real-world product performance at scale. SCG is evolving for an AI-enabled engineering environment, prioritizing how engineers think, reason, and complete tasks alongside advanced tools- not just narrow specialization. The SCG ArchDesign team is hiring a Senior Power Integrity Co-Design Engineer to architect and deliver di/dt mitigation across silicon, package, board, and platform. This role bridges architecture, silicon, and platform — translating product noise targets into shipped specs, and feeding silicon findings back into the next generation's design. Success in this role requires strong systems thinking and becoming comfortable with ambiguity. It also requires the ability to apply AI as a force multiplier while maintaining rigorous engineering judgment.

Requirements

BS, MS, or PhD in EE, CE, or related (or equivalent experience) with 12+ years in silicon power integrity, voltage noise, or PDN
Deep expertise in at least one of: di/dt analysis and mitigation, voltage droop, PDN design (die + package + board), transient noise, or decap budgeting.
Hands-on silicon experience: bring-up, characterization, correlation — comfortable on a bench with scopes, probes, and DAQ, and in front of a simulator.
Strong Sim-to-Si correlation instincts — the rigor of knowing which side of the equal sign is wrong, and the independence to say so.
Proven use of AI techniques to accelerate power integrity work includes noise modeling, transient prediction, Sim-to-Si analysis, and automated correlation checks.
Clear judgment is required to know where the model is conscientious and where manual measurement is vital.
Multi-functional collaboration and spec subject area: able to drive a decision through multiple partners, detail it, and own it through sign-offs.

Nice To Haves

Proof of craft: patents, publications, or reusable methodology you built in power integrity, PDN, or di/dt — artifacts that show how you think, not just what you shipped.
Hands-on experience with groundbreaking GPU, CPU, or AI accelerator silicon at advanced nodes; multi-rail, multi-domain PDN ownership at SoC level (die + package + board co-optimization in production).
A track record of applying ML or AI to noise modeling, transient prediction, droop response, or feature optimization — with the validation rigor to know when the model is wrong.
The best engineers on this team can describe a noise trade-off they made that nobody else in the room had yet framed.

Responsibilities

Define product-level voltage noise targets, drive them to closure, and sign them off at shipment.
Architect voltage noise mitigation across the full stack - silicon, package, board, platform - and lead the codesign tradeoffs between them.
Co-design noise features with Speed/Power/Reliability, circuit, power-arch, ASIC, and platform teams.
Build and lead the Sim-to-Si correlation methodology for voltage noise.
Model and prototype next-gen noise features - transient sense, droop response, mitigation IP.
Lead show-stopper noise bugs during bringup.
Drive architecture-level codesign tradeoffs across V/F ↔ Power ↔ Noise ↔ Reliability ↔ Thermal boundary work, where the highest-leverage innovation lives.