Senior Physical Design Engineer

Microsoft•Raleigh, NC

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) supports Microsoft’s cloud infrastructure and online businesses. Within SCHIE, the Compute Silicon & Manufacturing Engineering organization designs, develops, manufactures, and packages Microsoft chips, including Azure Cobalt. The team works to deliver cloud hardware infrastructure on time, at scale, with high quality, low cost, and sustainability in mind. The Senior Physical Design Engineer will contribute to silicon design and own physical-design execution for medium to large SOC blocks. The role covers RTL-to-GDS implementation, from synthesis through place-and-route and all required signoff stages. The engineer will work closely with CAD, RTL/design, DFT, architecture, power and performance, technology, and other internal and external partners to improve designs, tools, flows, and methodologies.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a master's degree in one of these fields and at least 4 years of technical engineering experience; or a bachelor's degree in one of these fields and at least 5 years of technical engineering experience; or equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
Ability to satisfy export-control eligibility verification requirements, including providing proof of citizenship, U.S. residency, or other protected status as applicable.

Nice To Haves

At least 7 years of semiconductor design experience.
Communication, collaboration, and teamwork skills, including the ability to contribute to diverse and inclusive teams.
A track record implementing designs through synthesis, floorplanning, place-and-route, extraction, timing, and physical verification.
Production silicon tape-out experience in advanced foundry process nodes.
Experience with low-power design methodology for SOCs.
Thorough understanding of SOC or subsystem design trade-offs across power, performance, and area (PPA).
Familiarity with clock-construction strategies for high-speed designs.
Technical expertise across physical design, from synthesis and place-and-route of partitions through timing signoff, physical verification, EMIR signoff, formal equivalence, and low-power verification.
Problem-solving and data-analysis skills.
Ability to communicate effectively with cross-functional teams.

Responsibilities

Drive end-to-end execution from synthesis through place-and-route for large designs, completing signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
Own clock construction and clock-tree synthesis (CTS).
Explore methodologies to optimize SOC blocks for clock construction and related methodology.
Coordinate with CAD, RTL/design, DFT, architecture, power and performance, technology, and other internal and external partners.
Implement RTL-to-GDS designs in the physical-design domain.
Use data-driven approaches to influence design tools, flows, and methodologies for construction, signoff, and optimization.
Collaborate across teams to deliver solutions aligned with a One Microsoft mindset.
Demonstrate technical expertise across physical-design domains and communicate project status and planning clearly.
Own complete physical-design execution for medium to large SOC blocks and provide hands-on technical ownership while collaborating across teams.
Partner with physical-design flow/CAD and methodology teams to identify and resolve PD TFM issues.
Demonstrate Microsoft core values, including customer focus, adaptability, collaboration, growth mindset, drive for results, influence for impact, judgment, and diversity and inclusion.