Senior Physical Design Engineer(7051)

TSMC•West Covina, CA

14d•$120,000 - $160,000•Hybrid

About The Position

As a Senior Physical Design and Verification Engineer, you will focus on high-performance block-level design, verification, and physical sign-off. You will own the resolution of complex DRC, LVS, ERC, and Antenna violations, mitigate EMIR and Noise issues, and implement timing ECOs. While your day-to-day focus will be at the block level, you will maintain close alignment with full-chip integration requirements to ensure seamless top-level assembly. In this role, you will work full-time on-site at a premier customer location in the South Bay (operating on a highly flexible 3-day in-office, 2-day remote hybrid schedule). You will join a dedicated team pushing the absolute limits of silicon technology, working directly on the world's most advanced A14 technology node.

Requirements

Master’s degree in Electrical Engineering (EE), Computer Science (CS), or a related field.
4+ years of hands-on industry experience in block-level physical design and physical verification.
Deep understanding of VLSI design, digital integrated circuits, logic design, DFT, computer architecture, and design automation.
Strong proficiency with industry-standard EDA tools and design flows (Synopsys, Cadence, or Siemens/Mentor Graphics).
Solid scripting skills in TCL and Perl for design flow automation.
Ability to work full-time at a customer site in the South Bay area on a hybrid schedule (3 days in-office, 2 days remote). No additional travel required.

Nice To Haves

Hands-on experience with advanced process nodes; experience with TSMC N7/N5/N3/N2 is highly desirable.
Highly skilled in developing custom TCL scripts to manipulate physical objects within P&R databases (e.g., Innovus or ICC2).
Strong understanding of chip-level integration constraints, low-power implementation methodologies (UPF/CPF), and interface requirements.
Demonstrated ability to independently own and complete block-level Netlist-to-GDSII P&R and sign-off tasks.

Responsibilities

Lead physical verification runs (DRC, LVS, ERC, Antenna) on complex blocks and resolve violations to achieve tape-out ready sign-off.
Perform block-level Power IR/EM and Signal EM/Noise analysis, implementing robust fixes.
Analyze block-level floorplans to resolve congestion, routability, and density issues.
Design and implement customized, high-performance clock tree structures within your blocks.
Implement functional and timing ECOs on high-performance blocks.
Independently drive Netlist-to-GDSII Place and Route (P&R) tasks through to completion.
Develop and utilize custom TCL/Perl scripts to automate design flows and manipulate physical objects within the P&R environment.