Senior Physical Design Engineer

Microsoft•Raleigh, NC

13d•$119,800 - $261,000

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is responsible for powering Microsoft’s “Intelligent Cloud” mission by delivering the core infrastructure and foundational technologies for Microsoft's over 200 online businesses. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE designs, develops, manufactures, and packages Microsoft's state-of-the-art computer chips, such as the Azure Cobalt. As Microsoft's cloud business grows, the ability to deploy new offerings and hardware infrastructure on time, in high volume, with high quality, and at the lowest cost is crucial. The CSME team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving planning processes, quality, delivery, scale, and sustainability related to Microsoft cloud hardware. We are seeking engineers with a passion for customer-focused solutions and industry insight to envision and implement future technical solutions for managing and optimizing cloud infrastructure. This role is for a Sr. Physical Design Engineer.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements.
Must pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Must provide proof of country of citizenship or US residency or other protected status for assessment of eligibility to access export-controlled information.
Citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Nice To Haves

BS/MS in Electrical or Computer Engineering or any related degree
Preferred 8+ years of experience in semiconductor design.
Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
Proven track record in Physical Design domain implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.
Experience in hierarchical design work, Design Planning and integration with multiple production tape-outs using advanced foundry process nodes.
Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff, Formal Equivalence, and Low Power Verification.
Own complete PD execution of Critical blocks/Partitions/Sub-systems/Sub-chips instantiating/integrating multiple other Physical partitions. Be fully hands-on in your individual ownerships as individual contributor and collaborate cross-team as required.
Proficient in integration activities and design planning (DP) methodology with hands-on experience.
Good understanding of timing constraints (functional & DFT), static timing analysis (STA), and timing-power optimization.
Thorough understanding of SOC or subsystem design trade-offs across power, performance, and area (PPA).
Hands-on experience with clock tree synthesis (CTS) and global clock distribution in complex multi-voltage, multi-clock, multi-domain, and low-power designs.
Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues upfront and ensure those are fixed in the next PD TFM release from CAD or are updated in the design project layer (as appropriate).
Skilled in industry-standard EDA tools (Synopsys or Cadence).
Mentor engineers on technical aspects.
Advanced proficiency in Engineering Change Order (ECO) implementation for power and timing convergence, with solid knowledge of functional and DFT ECO closure methodologies.
Demonstrated ownership of deliverables and cross-functional teamwork.
Proven track record in mentoring, influencing teams, and driving alignment through clear and effective communication.
Analytical and problem-solving skills, complemented by advanced scripting capabilities in Perl, TCL, and Python.

Responsibilities

Experience and knowledge on Synthesis, RTL / DFT feedback , Timing Constraints.
Responsible for RTL to GDS implementation in Physical Design domain for production flagship projects.
Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners.
Influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach.
Demonstrate technical expertise across various domains of Physical Design & Timing Signoff.
Lead and manage floor-planning and design planning activities to optimize timing-critical and large sub-chips for power, performance, and area (PPA).
Drive end-to-end execution from synthesis through place-and-route for block execution, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
Make sound technical trade-offs between power, area, and timing to achieve optimal design outcomes.
Foster collaboration across teams to deliver solutions, aligned with a One Microsoft mindset.
Clear communications on project status & planning.
Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.