Senior Physical Design Engineer

EnCharge AI • Santa Clara, CA

13d

About The Position

We are seeking a highly experienced Senior Physical Design Engineer with a strong background in chip-level implementation and EDA tools. The ideal candidate will have deep expertise in physical design, timing closure, and low-power design.

Requirements

• 10+ years of experience in physical design (excluding other areas such as logic design or CAD)
• Strong understanding of EDA implementation for chip design
• Hands-on experience in Cadence tools
• Strong knowledge of timing concepts and timing closure techniques for chip design
• Experience with both top-level and block-level physical design
• Proficiency in low-power design concepts and debugging
• Experience with EM/IR checks, debugging, and issue resolution, including power grid verification
• Strong scripting skills in TCL or Python for automation
• Understanding of process concepts is needed for physical verification as part of routing tasks

Nice To Haves

• Experience with hierarchical floorplanning
• Experience with physical design methodology and flow setup
• Additional experience in areas such as PDK management or foundry tapeout processes

Responsibilities

• Chip-level implementation
• Physical design
• Timing closure
• Low-power design
• Top-level and block-level physical design
• EM/IR checks, debugging, and issue resolution, including power grid verification
• Automation using scripting languages
• Physical verification as part of routing tasks
• Advanced flow evaluations

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed