Senior Physical Design Engineer
About The Position
At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same. This is an onsite role based in Santa Clara, CA. As a Physical Design Engineer, you will work on complex digital and mixed-signal designs across advanced process technologies, helping drive designs from implementation through verification and tape-out. This role offers the opportunity to solve challenging physical design problems, collaborate with cross-functional engineering teams, and support next-generation IC product development using industry-leading methodologies and tools.
Requirements
- 10+ years of experience in Physical Design, with hands-on expertise supporting complex digital or mixed-signal IC implementation.
- Strong knowledge of physical design flows, including floor planning, clock tree synthesis, place and route, physical-aware synthesis, and design closure.
- Experience developing power-grid strategies and high-speed clock constraints to support performance, power, and area goals.
- Working knowledge of physical verification methodologies, including LVS and DRC debug at chip and block levels.
- Familiarity with CDC, static timing analysis methodologies, SDF-annotated simulations, and parasitic delay impact.
- Exposure to mixed-signal design environments and the interaction between digital implementation and analog/layout requirements.
- Hands-on experience with tools such as Virtuoso, Calibre, RedHawk, or similar EDA platforms.
- Understanding of design tape-out processes, foundry requirements, and the semiconductor product development supply chain.
Nice To Haves
- Experience estimating design and layout effort for digital blocks in advanced-node technologies.
- Strong understanding of power, performance, and area tradeoffs in leading-edge process technologies.
- Prior experience supporting full-chip or block-level tape-out to foundries.
- Ability to work collaboratively across multiple engineering disciplines and communicate technical tradeoffs clearly.
- Experience with advanced TSMC process nodes, such as 7nm through 2nm, is highly preferred.
Responsibilities
- Support the implementation and optimization of advanced-node semiconductor designs.
- Lead or support physical design activities, including floor planning, placement, clock tree synthesis, routing, and physical-aware synthesis.
- Develop and implement power-grid strategies, high-speed clock constraints, and design specifications to support performance, power, and area goals.
- Perform physical design verification and debug LVS and DRC issues at both chip and block levels.
- Collaborate with design, layout, verification, timing, and methodology teams to address implementation challenges across the design lifecycle.
- Support CDC, static timing analysis, parasitic-aware simulation, and timing closure activities using relevant EDA tools and methodologies.
- Contribute to tape-out readiness, including design signoff, foundry interaction, and alignment with IC product development requirements.
- Evaluate design tradeoffs related to power consumption, area, performance, layout complexity, and technology limitations for advanced process nodes(3nm /5nm/7nm
Benefits
- Medical, dental, and vision coverage
- Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada)
- Life and disability insurance
- Employee assistance programs
- Paid time off based on employee grade (A-F), defined by policy: Vacation: 12-25 days, depending on grade, Company paid holidays, Personal Days, Sick Leave
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What This Job Offers
Job Type
Full-time
Career Level
Senior
Education Level
No Education Listed
