Senior Physical Design Engineer

Microsoft•Hillsboro, OR

22h

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) powers Microsoft’s cloud infrastructure and supports more than 200 online businesses and services, including Azure, Office 365, Teams, Xbox Live, Bing, MSN, and OneDrive. Its Compute Silicon & Manufacturing Engineering (CSME) organization is responsible for designing, developing, manufacturing, and packaging Microsoft computer chips, including Azure Cobalt. The organization works to deliver cloud hardware at scale with high quality, on time, and at low cost, while improving operational performance and sustainability. The Senior Physical Design Engineer will contribute to silicon design and own physical-design execution, including RTL-to-GDS implementation and end-to-end execution from synthesis through place-and-route. The role includes completing signoff activities, constructing clocks, exploring methodologies to optimize SoC blocks, and collaborating with cross-functional teams and partners. The engineer will help influence tools, flows, and methodologies through data-driven work, communicate project status and plans, and contribute in alignment with Microsoft’s customer-focused, collaborative, adaptable, growth-oriented, and inclusive values.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a master’s degree in one of these fields and at least 4 years of technical engineering experience; or a bachelor’s degree in one of these fields and at least 5 years of technical engineering experience; or equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
Ability to provide proof of citizenship, U.S. permanent residency, or other protected status for assessment of eligibility to access export-controlled information; citizenship is verified with a valid passport, with alternative documents available where applicable for lawful permanent residents, refugees, and asylees.

Nice To Haves

Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related field.
At least 7 years of experience in semiconductor design.
Strong communication, collaboration, and teamwork skills, with the ability to contribute to diverse and inclusive teams.
Proven physical-design experience implementing designs through synthesis, floorplanning, place-and-route, extraction, timing, and physical verification.
Production silicon tape-out experience in advanced foundry process nodes.
Experience with low-power design methodology for SoCs.
Thorough understanding of SoC or subsystem design trade-offs across power, performance, and area (PPA).
Familiarity with clock-construction strategies for high-speed designs.
Technical expertise across physical design, from synthesis to place-and-route of partitions and through timing signoff, physical verification, EMIR signoff, formal equivalence, and low-power verification.
Experience owning complete physical-design execution of a medium- to large-sized SoC block.
Ability to provide hands-on individual-contributor technical ownership and collaborate across teams.
Experience partnering with PD flow/CAD and PD methodology teams to identify and resolve PD TFM issues.
Problem-solving and data-analysis skills.
Ability to communicate effectively with cross-functional teams.

Responsibilities

Drive end-to-end execution from synthesis through place-and-route for large designs, completing signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
Own clock construction and clock-tree synthesis (CTS).
Drive methodology exploration to optimize SoC blocks for clock construction and related methodologies.
Coordinate with CAD, RTL/design, DFT, architecture, power and performance, technology, and other internal and external partners.
Perform RTL-to-GDS implementation in the physical-design domain.
Influence design tools, flows, and methodologies for construction, signoff, and optimization using a data-driven approach.
Collaborate across teams to deliver solutions aligned with a One Microsoft mindset.
Demonstrate technical expertise across physical-design domains.
Communicate project status and planning clearly.
Demonstrate Microsoft core values, including customer focus, adaptability, collaboration, growth mindset, drive for results, influence for impact, judgment, and diversity and inclusion.