Senior PCB Design Engineer

Arista Networks•Santa Clara, CA

1d•$133,000 - $180,000

About The Position

Arista Networks is seeking a Senior PCB Design Engineer to join their Hardware Design Engineering team. This role involves developing high-speed networking and Ethernet products for enterprise campuses, hyperscale datacenters, and next-generation AI clusters. The team is responsible for the end-to-end design and development of advanced hardware solutions, including optical interface platforms up to 800G and 1.6T. The engineer will work closely with cross-functional teams including Hardware Design, Signal Integrity (SI), Power Integrity (PI), Mechanical Engineering, Thermal Engineering, and Manufacturing to innovate on system architectures and ultra-high-speed PCB designs.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or related field
10+ years of relevant hardware engineering experience
Proven experience designing networking hardware, particularly involving 100G/200G PAM4 Ethernet switching
Direct experience in high-speed optical transceiver PCB layout (800G and/or 1.6T preferred)
Expertise with 112G / 224G PAM4 routing and channel optimization
Advanced proficiency in Cadence Allegro and Sigrity
Experience designing 20+ layer boards with 50G+ signals
Hands-on experience with sequential lamination, HDI, ultra-low-loss materials
Experience in multi-phase DC/DC layout for high-current, high transient loads
Strong manufacturing knowledge including DFM, DFA, and DFT for 30+ layer rigid and rigid-flex boards
Demonstrated success taking products from concept through mass production

Nice To Haves

800G and/or 1.6T optical transceiver PCB layout experience

Responsibilities

Implement complex routing for advanced interfaces such as 112G/224G SerDes, PCIe Gen 5/6, DDR4/5/6
Design and route high-speed differential pairs with tight skew and impedance control
Execute dense BGA fan-out for high-pin-count ASICs and FPGAs
Design and layout boards supporting high-bandwidth optical transceivers (QSFP-DD, OSFP, OSFP-XD or equivalent)
Route 112G / 224G PAM4 electrical channels between switch ASICs and optical modules
Define insertion loss budgets and coordinate with SI engineers to meet IEEE compliance requirements
Optimize breakout routing beneath high-density optical cages
Implement via stub mitigation strategies including backdrilling for ultra-high-speed signal paths
Manage ground reference continuity, EMI control, and return path integrity near optical connectors
Consider thermal dissipation (20W–30W+ modules) in layout planning
Design advanced multi-layer stack-ups (20–30+ layers)
Calculate impedance profiles and ensure low-reflection, low-crosstalk performance
Collaborate with SI teams on channel modeling and pre-/post-layout simulations
Design robust Power Distribution Networks (PDNs) for high-current ASICs
Layout multi-phase DC/DC converters for high transient loads
Strategically place decoupling capacitors to ensure wideband impedance stability
Integrate thermal vias, heat sink attachments, and high-conductivity materials
Coordinate mechanical constraints such as enclosure, airflow, and structural limitations
Ensure proper placement and structural integration of optical cages
Generate comprehensive manufacturing packages (Gerber, ODB++, IPC-2581)
Define backdrilling parameters and impedance specifications
Ensure compliance with DFM, DFA, and DFT requirements
Support boards through fabrication, assembly, and production ramp
Create and maintain high-density component footprints (e.g., large BGAs, optical module connectors)
Participate in new product feasibility studies
Develop detailed routing guidelines and work packages for layout partners
Review external placement and routing work to ensure quality and schedule adherence