Senior Mask Layout Engineer

IonQ•College Park, MD

5d•$126,887 - $166,127•Hybrid

About The Position

IonQ is seeking a Senior Mask Layout Engineer to join the Fab Tapeout and Validation Team. This role is crucial for building the world's best quantum computers. The engineer will be responsible for full-reticle tapeouts for trapped-ion quantum computers, including photonic and analog electronic layers. Responsibilities also include developing and maintaining internal PDK and circuit layout libraries, scripting for mask layout automation, and collaborating with design and testing teams to advance quantum technology.

Requirements

Bachelor’s degree in Photonics, Physics, Electrical Engineering, or related field, or equivalent practical experience
Knowledge of semiconductor manufacturing processes and techniques
Excellent programming and software skills, including development in an IDE, proficiency with version control software, shell scripting, and code documentation
2+ years of experience with Python-based mask layout software packages such as Luceda IPKISS, GDSFactory, or Klayout

Nice To Haves

M.S. or Ph.D. in Photonics, Physics, Electrical Engineering, or related field
5+ years experience in generating layout files for complex semiconductor flows with custom elements, such as MEMS, integrated photonics, or superconducting circuits
Past ownership of full-reticle tapeouts with commercial foundries
Experience with commercial simulation, verification, and layout environments such as Synopsys, Cadence, and Ansys
Familiarity with photonic and/or analog electronic device principles including design, test, and fabrication
Proficiency in physical verification including DRC, LVS, and ERC
Experience with semiconductor and/or photonic workflows for tapeout with commercial foundries
Excellent verbal and written communication skills
A meticulous attention to detail and excellent track record of documenting requirements, implementation plan, and tracking progress
Ability to work independently, prioritizing tasks and managing time effectively in a deadline-oriented environment

Responsibilities

Conduct Python-based layout for full-reticle tapeouts with commercial foundries
Develop and maintain internal component PCell and automated circuit layout libraries
Interface with designers, test engineers, packaging engineers, and foundry team to define layout rules and component designs
Implement physical verification checks of layouts, including DRC and LVS
Develop detailed documentation of tapeouts and lead layout reviews with other team members
Work with cross-functional teams to understand circuit requirements and make recommendations to improve design, layout, and test workflows