Senior Mask Design Engineer – Hardware

NVIDIA•Us, CA

4d•Hybrid

About The Position

NVIDIA's GPUs and SOCs are the world leaders in power, performance, and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Mask Design Engineer who is committed to making a difference in the world through their contributions! This position will collaborate with Package Technical Lead and different design teams in designing and developing sophisticated, detailed layout of silicon interposers for NVIDIA products. In addition, work with design teams to plan schedules, resolve costs, manufacturing, and electrical design issues.

Requirements

Hold a B.S. Electrical Engineering or equivalent experience
Minimum of 5+ years proven experience in Mask and Layout Design.
Deep understanding of layout concepts in submicron CMOS technologies.
Authority with Cadence layout tools - particularly Virtuoso.
Experience running and debugging with verification tools such as Calibre, ICV, Thunder, etc.
Proficient in scripting languages like Perl, Python, Skill, etc.
Should have knowledge of DRC and LVS checking flows, ability to customize decks.
Good understanding of packaging technology is useful.
Ability to work optimally in a team, good interpersonal skills, passion and positive energy.

Nice To Haves

Knowledge of Integrity auto-routing is a plus.
Knowledge of APD package layout tool is a plus.

Responsibilities

Collaborate cross functionally with package technical lead (PTL) and I/O signal integrity and technology engineers to deliver solution for product packages in tight schedule.
Performing physical layout for silicon interposer using Cadence tools.
Conduct design feasibility studies to evaluate the package design goals for size, cost, and system performance.
Take part in studying layout floorplan and perform custom layout and verification against design rules and netlists.
Propose layout design trade-offs to the PTL for resolution and implementation.