Senior Manager, Performance Engineering – Kernel and Software Platforms

NVIDIA•Santa Clara, CA

1d•$272,000 - $488,750•Hybrid

About The Position

NVIDIA’s accelerated computing platform relies on continuous performance excellence at every stage of development. We are seeking an outstanding Performance Analysis Manager to lead an engineering team responsible for supervising and optimizing product performance throughout the full hardware lifecycle. In this role, you will bridge the gap between design-time predictions and real-world execution: evaluating performance from early simulation and emulation, through post-silicon bring-up, to production hardware and ongoing release support. Your role involves analyzing kernel authoring flows from DSLs to internal code representations. You will set expectation models, curate workload testlists, and coordinate with CUDA release schedules. Additionally, you will promote automation with AI tools such as Claude and Codex.

Requirements

MS or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related field, or equivalent experience.
10+ overall years of experience in systems/software performance engineering, platform benchmarking, or a related area.
5+ years of experience leading or managing technical engineering teams.
Demonstrated track record tracking performance through the entire hardware pipeline—from design-time simulation/emulation infrastructure to early post-silicon bring-up and deployed production hardware.
Proven track record to build expectation models and correlate simulation predictions with physical hardware telemetry without needing to be a daily low-level kernel developer.
Understanding of modern kernel compilation pipelines, compiler flows (DSL -> IR -> target code), and how high-level software abstraction impacts low-level execution efficiency.
Experience developing workload testlists to detect performance regressions and aligning performance delivery with major software release cycles (e.g., CUDA cadence).
Proficiency in Python automation with practical experience employing generative AI APIs/models (Codex, Claude, custom agents) to automate triage and analytical workflows.

Nice To Haves

Experience building automated "shift-left" performance validation frameworks that map pre-silicon simulator data directly against post-silicon measurements.
Hands-on analytical experience with intermediate representations (MLIR, LLVM IR, NVVM/PTX) to identify performance loss between abstraction layers.
Proven success designing LLM-driven agents that automatically analyze performance regressions between hardware software releases and summarize root causes.

Responsibilities

Supervise and maintain continuous performance tracking for GPU software products from pre-silicon build time, simulation, and emulation environments through initial post-silicon validation, product hardware, and post-release maintenance.
Architect theoretical and empirical performance models to set targets early in design. Continuously correlate pre-silicon simulation predictions against early hardware and production silicon to diagnose and eliminate discrepancies.
Evaluate and benchmark performance translation across diverse kernel authoring flows—analyzing code efficiency from high-level DSLs (e.g., Triton, PyTorch) through compiler Intermediate Representations (IRs) down to target hardware execution across every phase of platform maturity.
Identify, craft, and maintain stress-test suites and workload testlists representative of production applications. Use these testlists to stress system performance, detect regressions early in simulation, and validate hardware release candidates.
Work multi-functionally with compiler, architecture, and platform software teams to ensure performance achievements hit target expectations on schedules strictly linked to the CUDA release timeline.
Integrate modern AI infrastructure (e.g., Claude, OpenAI Codex, agentic LLM workflows) to automate telemetry analysis, root-cause pre-vs-post silicon performance deltas, and streamline performance reporting pipelines.