Senior Lead Engineer - Design and Architecture

Altera•San Jose, CA

1d•$231,500 - $330,000

About The Position

Altera is seeking a Senior Lead Engineer, Design and Architecture to provide technical leadership for the architecture and development of high-performance silicon and platform subsystems across its programmable device portfolio. This is a senior individual-contributor role for a hands-on architect and design leader who can define complex SoC and interconnect solutions, drive critical design decisions, and guide execution from early concept through production silicon. The successful candidate will bring deep expertise in ASIC/SoC architecture, high-bandwidth interconnect, memory systems, and networking or infrastructure-class silicon. They will partner closely with architecture, RTL design, verification, emulation, physical design, software, and post-silicon teams to deliver scalable, performant, and manufacturable solutions for AI, cloud, networking, and edge applications. The position is based in San Jose, California. The stated salary range applies to the Bay Area, California: $231,500–$330,000. Actual salary may vary based on factors including job location, job-related knowledge, skills, experience, and training. Incentive opportunities reward employees based on individual and company performance. Altera uses artificial intelligence to screen, assess, or select applicants. Applicants must be eligible for any required U.S. export authorizations.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
15+ years of experience in semiconductor, ASIC, SoC, or FPGA product development.
Demonstrated experience defining and delivering complex silicon architectures from concept through production, including architecture, microarchitecture, RTL design, verification, integration, and post-silicon validation.
Deep expertise in one or more of the following: on-chip networks, coherent or non-coherent interconnect, memory hierarchy, cache coherency, high-performance networking datapaths, packet processing, or infrastructure-class SoC design.
Strong understanding of architectural tradeoffs involving bandwidth, latency, congestion, throughput, power, area, timing, and reliability.
Experience working across the silicon development lifecycle with design, verification, emulation, physical design, DFT, firmware/software, and post-silicon teams.
Proven technical leadership driving complex cross-functional decisions, resolving ambiguous problems, and influencing engineering teams without direct management authority.

Nice To Haves

Master’s degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Experience delivering advanced-node, high-complexity SoCs or ASICs into production for networking, cloud, AI/ML, communications, storage, security, or data-center infrastructure applications.
Experience architecting scalable Network-on-Chip or fabric solutions, including topology, routing, arbitration, quality of service, traffic management, credit-based flow control, and performance analysis.
Experience with memory systems, cache hierarchy, coherency protocols, HBM/DDR integration, or high-bandwidth data movement.
Working knowledge of RTL and verification methodologies, such as SystemVerilog, simulation, formal verification, emulation, or equivalence checking, and familiarity with synthesis, static timing, and implementation flows.
Experience with architecture modeling, performance analysis, Python-based automation, or AI-assisted engineering workflows that improve specification quality, debug, or design productivity.
Experience with programmable logic devices, heterogeneous SoC platforms, or the integration of hard and soft IP across multiple product generations.
Record of technical innovation demonstrated through patents, publications, major product contributions, or industry leadership.

Responsibilities

Define system, subsystem, and microarchitecture for complex SoC, ASIC, and FPGA-adjacent platforms, emphasizing high-performance interconnect, data movement, memory hierarchy, and scalable compute or networking subsystems.
Lead architecture exploration and make technically sound tradeoffs across performance, power, area, bandwidth, latency, reliability, scalability, cost, and schedule.
Develop architectural specifications, performance models, and implementation plans that align requirements across hardware, firmware, software, validation, and product teams.
Own key architecture and design decisions through the full silicon lifecycle, from concept and microarchitecture through RTL, integration, verification, emulation, implementation, bring-up, performance debug, and production readiness.
Provide hands-on technical leadership for on-chip networks, routing and arbitration, flow control, cache or memory-coherency mechanisms, memory subsystems, and high-speed interfaces, as applicable to the product roadmap.
Drive cross-functional resolution of complex technical issues, using data and rigorous analysis to identify root causes, evaluate alternatives, and close critical architectural or execution risks.
Partner with design, verification, physical design, DFT, firmware, software, product engineering, and manufacturing teams to preserve architecture intent through implementation and silicon validation.
Establish and improve scalable design and verification methodologies, automation, and quality practices that increase engineering velocity, predictability, and first-pass silicon success.
Mentor senior engineers and technical leads, raise the technical bar through reviews and design guidance, and influence engineering direction across multiple teams and product generations.
Engage with internal and external partners, including IP, EDA, and foundry providers, as needed to inform architecture, implementation strategy, and roadmap planning.