Senior Implementation Methodology Engineer

NVIDIA•Santa Clara, CA

2d•$168,000 - $264,500

About The Position

NVIDIA is seeking a skilled and motivated Implementation Methodology Engineer for its elite VLSI team. This role involves owning synthesis methodology development in the RTL2GDS pipeline and supporting advanced-node chip development. The engineer will lead aggressive PPA optimization campaigns and invent next-generation efficiency automation that multiplies engineering throughput across build teams. This role offers an outstanding chance to create lasting impact in silicon engineering for individuals who thrive at the intersection of physical design methodology, data-driven optimization, and scalable automation.

Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent experience.
6+ years of hands-on proven experience in ASIC implementation methodology and EDA tool/flow development.
Deep, practical expertise in the complete RTL2GDS flow: synthesis, DFT, floorplanning, placement, CTS, routing, and MCMM STA.
Power user of synthesis and place-and-route tools from Synopsys (DC/FC, ICC2, PrimeTime) and/or Cadence (Genus, Innovus, Tempus).
Prior experience in data-focused EDA tool evaluation, flow benchmarking, and methodology development with demonstrated PPA impact.
Strong scripting proficiency in Python, TCL, Perl, and/or Make for flow automation and analysis.
Demonstrated ability to drive complex, cross-functional technical initiatives — aligning build, CAD, and EDA vendor teams toward shared goals.
Excellent problem-solving, debugging, and analytical skills with a track record of simplifying complex, cluttered environments.
Strong interpersonal and communication skills; able to translate technical findings into actionable recommendations for diverse audiences.

Nice To Haves

Demonstrated application of AI/ML or GenAI techniques to physical build, QoR analysis, flow automation, or design space exploration — in production or research contexts.
Solid understanding of front-end flows and methodology: RTL build intent, DFT insertion, synthesis constraints, and UPF/CPF low-power build — enabling an end-to-end perspective.

Responsibilities

Own and continuously improve the end-to-end RTL2GDS implementation methodology — covering synthesis, place & route, CTS, and equivalence checking — for advanced-node CPU builds.
Evaluate new EDA tools and process node capabilities and deliver clear adoption recommendations.
Serve as the technical liaison between internal teams and EDA vendors (Synopsys, Cadence) to resolve tool issues and influence vendor roadmaps.
Define and enforce implementation methodology BKMs and flow standards across development teams; maintain user documentation and lead training on tools and flows.
Build and complete rigorous A/B and multi-variant experiments to quantitatively compare flows, engine settings, and optimization strategies for QoR impact.
Drive aggressive PPA targets throughout the full implementation cycle.
Conduct deep root-cause analysis on timing closure bottlenecks, power limiters, and long-tail QoR issues, and develop methodologies to resolve these problems at scale.
Architect and build Python/TCL/Perl automation frameworks that reduce manual engineering effort and improve design turnaround time across implementation teams.
Identify systemic efficiency bottlenecks across the implementation flow and eliminate them through targeted automation, data-driven regression infrastructure, and AI/ML-assisted flow optimization.
Partner with architecture, RTL, DFT, physical build, and sign-off teams to surface PPA opportunities early and translate methodology improvements into measurable silicon impact.