Senior DFX Power Methodology Engineer

NVIDIA•Santa Clara, CA

6d•$196,000 - $368,000

About The Position

Design-for-X Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions in AI for Chip Design and AI for Predictions in various use cases in manufacturing testing on some of the industry's most complex semiconductor chips.

Requirements

BSEE (or equivalent experience) with 12+, MSEE with 10+, or PhD with 6+ years of experience in DFT design & power
Understanding of fundamental DFT topics and VLSI areas of power, timing & voltage noise
Excellent knowledge in using statistical tools for data analysis & insights.
Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power.
Experience in Silicon debug and bring-up on the ATE or SLT platforms.
Be able to think like a programmer so that this can be translated into action using AI Coding harnesses
Outstanding written and oral communication skills with the curiosity to work on rare challenges.

Nice To Haves

Experience in Power Analysis, Thermal Analysis & IR Drop tools is a plus.
Experience in application of AI for EDA-related problem-solving is a plus.
Experience in managing DFT Power Methodology for designs
Experience in post-silicon debug for thermal & IR Drop
Good understanding of technology and passionate about what you do
Strong collaborative and interpersonal skills, specifically a proven ability to effectively guide and influence within a dynamic environment

Responsibilities

Innovating in the DFX Power, Thermal & Voltage Noise Methodology areas.
Working on groundbreaking low power & thermal solutions for manufacturing tests to be enabled at conditions that push the boundaries for datacenter GPUs.
Working with multi-functional teams including Product Development & Power Architecture, implementing brand-new methodologies on hard-to-solve problems for improving outgoing quality of chips.
Working on post-silicon data analysis for power to architect next-gen solutions.
Developing and deploying DFT methodologies for next generation products using Applied ML & Gen AI solutions.
Mentoring junior engineers on test designs and trade-offs including cost and quality.