Physical Design Methodology Engineer

Intel Corporation•Austin, TX

2d•$164,470 - $269,100•Hybrid

About The Position

Advanced Design and Foundational IP (ADFIP) is part of Design Technology Platform (DTP) under Foundry Technology Development. ADFIP's core focus is design-technology co-optimization (DTCO), system-design co-optimization (STCO) and foundational IP development to support Intel technology development, internal client/server/NEX products and external tier0/tier1 customers. The organization develops logic libraries, memories, high-speed I/Os, analog and mixed signal IPs, RF/mm Wave circuits and 3D IC, and conducts comprehensive Si validation on process and package development test vehicles and FIP characterization vehicles. Advanced power, performance and area (PPA) analysis are conducted across domains to guide silicon and packaging technology definition to maximize technology PPA entitlement and minimize process risks and cost. As a process technology design engineer, you will be responsible for creating methodologies, models, and flows for advanced design rules for a specific process node and characterizes those models through silicon validation. Ensures IP and SoC design meets requirements and standards for a specific manufacturing process technology. Identifies ways to optimize silicon designs by evaluating device performance over a range of operating conditions. Resolves prototype issues and determines whether problems are design or process related. Conducts experiments to identify potential challenges in the process and ensure that the process meets yield, quality, and reliability standards. Drives continuous improvements to enhance the designs, materials, and methodologies. Disseminates process development information to design groups, ensures it meets future product requirements, and extracts necessary technical and device performance data for IP and SoC designs. Works with IP and SoC design teams to capture and optimize process requirements to enable competitive designs and products.

Requirements

Bachelors with 6+ years of experience or master's degree in electrical engineering, Computer Engineering, or Computer Science with 4+ years of industry experience or PhD. with 2+ years of experience.
3+ years of experience with the following technical skills: Working knowledge of digital design and signoff.
Able to independently complete Netlist RTL-GDS place and route (APR), signoff tasks.

Nice To Haves

Strong technical understanding of semiconductor technology.
Working knowledge on Intel's leading process design rules.
Experience in working with BOTH Cadence and Synopsys EDA tool/flow
Demonstrated ability to work independently in a fast-paced environment.
Experience in optimizing PPA for low power designs such as GPU/AI

Responsibilities

Creating methodologies, models, and flows for advanced design rules for a specific process node.
Characterizing those models through silicon validation.
Ensuring IP and SoC design meets requirements and standards for a specific manufacturing process technology.
Identifying ways to optimize silicon designs by evaluating device performance over a range of operating conditions.
Resolving prototype issues and determining whether problems are design or process related.
Conducting experiments to identify potential challenges in the process and ensure that the process meets yield, quality, and reliability standards.
Driving continuous improvements to enhance the designs, materials, and methodologies.
Disseminating process development information to design groups, ensuring it meets future product requirements, and extracting necessary technical and device performance data for IP and SoC designs.
Working with IP and SoC design teams to capture and optimize process requirements to enable competitive designs and products.