Senior Hardware Engineer
About The Position
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) develops infrastructure and foundational technologies for Microsoft’s online services, Azure platform, and global server and data center infrastructure. The Methodology, Infrastructure, Silicon Engineering, and Labs engineering (MILE) team delivers the physical design CAD flows, tools, and infrastructure used to take advanced-node chips from RTL to tapeout. Within MILE, the Physical Design CAD signoff group owns logic signoff, including formal equivalency checking, ECO verification, and low-power verification. The Senior PD CAD Equivalency Engineer will own and evolve formal equivalency flows, working with silicon design teams and EDA vendors to deliver reliable equivalency checking for Microsoft’s next-generation silicon. The position owns end-to-end equivalency flows and production automation, supports tool qualification and issue resolution, and drives improvements in flow quality, runtime, and reliability. The role also makes technical decisions in the equivalency domain and mentors or backs up other engineers.
Requirements
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a master's degree in one of these fields and at least 4 years of technical engineering experience; or a bachelor's degree in one of these fields and at least 5 years of technical engineering experience; or equivalent experience.
- Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
- Must provide proof of citizenship, U.S. residency, or other protected status to assess eligibility for access to export-controlled information; citizenship is verified with a valid passport, with other applicable documents available for lawful permanent residents, refugees, and asylees.
Nice To Haves
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 3 years of technical engineering experience; or a master's degree in one of these fields and at least 6 years of technical engineering experience; or a bachelor's degree in one of these fields and at least 8 years of technical engineering experience; or equivalent experience.
- At least 5 years of experience in silicon CAD, physical design (logic synthesis), or design verification flows using tools such as Synopsys Fusion Compiler/Design Compiler and/or Cadence Genus/Innovus.
- At least 3 years of hands-on experience with formal equivalency checking tools (Synopsys Formality and/or Cadence Conformal) in advanced process nodes.
- Proficiency in Tcl and Python scripting and automation for developing and debugging production CAD flows.
- Experience with ECO flows, including functional-metal ECO and UPF-aware low-power equivalency verification.
- Experience qualifying and deploying EDA tool releases and working with vendor application engineers to resolve issues; familiarity with both Synopsys and Cadence equivalency tools.
- Effective communication and collaboration skills, including working with distributed design and CAD teams and translating complex tradeoffs into clear next steps.
- Experience supporting multiple concurrent tapeouts and familiarity with cloud-based EDA compute environments.
Responsibilities
- Own end-to-end formal equivalency CAD flows for RTL-to-netlist, netlist-to-netlist, functional ECO, and UPF-aware low-power verification across Microsoft silicon programs.
- Develop, debug, and maintain production flows and automation in Tcl and Python for Synopsys Formality and Cadence Conformal, including support for complex design classes.
- Partner with physical design, front-end/synthesis, signoff teams, and EDA vendors to qualify new tool releases, resolve critical tool issues, and support design teams through tapeout closure.
- Drive technical decisions for the equivalency domain, identify root causes of ambiguous tool behavior, and define paths to resolution.
- Mentor and serve as a backup for other engineers on the team.
- Improve flow quality, runtime, and reliability through regression coverage, documentation, and support turnaround for design teams.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
