Senior Hardware Engineer

Microsoft • Mountain View, CA

19h • $119,800 - $234,700

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) delivers infrastructure and foundational technologies for Microsoft’s online businesses and Azure platform. Within SCHIE, the Methodology, Infrastructure, Silicon Engineering, and Labs engineering (MILE) team provides physical-design CAD flows, tools, and infrastructure for silicon design teams. The Physical Design CAD signoff group owns logic signoff, including formal equivalency checking, ECO verification, and low-power verification. The flows help design teams establish functional correctness before tapeout, supporting schedule, cost, and silicon quality across Microsoft’s cloud and AI programs.

The role is described in the posting as Senior PD CAD Equivalency Engineer. It owns and evolves formal equivalency flows and works with design teams and EDA vendors to deliver reliable equivalency checking for Microsoft’s next-generation silicon. The position owns end-to-end formal equivalency CAD flows for silicon programs, develops and maintains production automation, supports tool qualification and issue resolution, drives technical decisions, mentors and backs up teammates, and improves flow quality, runtime, reliability, documentation, and support turnaround.

Requirements

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a master’s degree in one of these fields and at least 4 years of technical engineering experience; or a bachelor’s degree in one of these fields and at least 5 years of technical engineering experience; or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including passing a Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• Must meet export-control eligibility requirements for access to controlled information; the successful candidate must provide citizenship or qualifying residency/protected-status evidence, with citizenship verified using a valid passport where applicable.
• Preferred: Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 3 years of technical engineering experience; or a master’s degree in one of these fields and at least 6 years; or a bachelor’s degree in one of these fields and at least 8 years; or equivalent experience.
• Preferred: At least 5 years of experience in silicon CAD, physical design (logic synthesis), or design verification flows, using tools such as Synopsys Fusion Compiler/Design Compiler and/or Cadence Genus/Innovus.
• Preferred: At least 3 years of hands-on experience with formal equivalency checking tools such as Synopsys Formality and/or Cadence Conformal in advanced process nodes.
• Preferred: Proficiency in Tcl and Python scripting and automation for developing and debugging production CAD flows.
• Preferred: Experience with ECO flows, including functional-metal ECO and UPF-aware low-power equivalency verification.
• Preferred: Experience qualifying and deploying EDA tool releases and working with vendor application engineers to resolve issues; familiarity with Synopsys and Cadence equivalency tools.
• Preferred: Effective communication and collaboration skills, including working with distributed design and CAD teams and translating complex tradeoffs into clear next steps.
• Preferred: Experience supporting multiple concurrent tapeouts and familiarity with cloud-based EDA compute environments.

Nice To Haves

• At least 5 years of experience in silicon CAD, physical design (logic synthesis), or design verification flows using Synopsys Fusion Compiler/Design Compiler and/or Cadence Genus/Innovus.
• At least 3 years of hands-on experience with Synopsys Formality and/or Cadence Conformal in advanced process nodes.
• Proficiency in Tcl and Python scripting and automation for production CAD flows.
• Experience with functional-metal ECO and UPF-aware low-power equivalency verification.
• Experience qualifying and deploying EDA tool releases and working with vendor application engineers to drive issue resolution; familiarity with both Synopsys and Cadence equivalency tools.
• Effective communication and collaboration with distributed design and CAD teams, and ability to translate complex tradeoffs into clear next steps.
• Experience supporting multiple concurrent tapeouts and familiarity with cloud-based EDA compute environments.
• Preferred education and experience: doctorate plus 3 years, master’s plus 6 years, bachelor’s plus 8 years of technical engineering experience, or equivalent experience.

Responsibilities

• Own end-to-end formal equivalency CAD flows, including RTL-to-netlist, netlist-to-netlist, functional ECO, and UPF-aware low-power verification.
• Develop, debug, and maintain production flows and automation in Tcl and Python for Synopsys Formality and Cadence Conformal, including for complex design classes.
• Partner with physical design, front-end/synthesis, and signoff teams, as well as Synopsys and Cadence, to qualify tool releases, resolve critical tool issues, and support design teams through tapeout closure.
• Drive technical decisions for the equivalency domain, identify root causes of ambiguous tool behavior, and define paths to resolution.
• Mentor teammates and serve as a backup for other engineers on the team.
• Improve flow quality, runtime, and reliability, including regression coverage, documentation, and support turnaround for design teams.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior