Senior Hardware Engineer - Micro-Architect
About The Position
Quadric is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable architecture. Our technology powers intelligent edge devices across automotive, industrial, robotics, and embedded systems. Founded in 2016 and based in downtown Burlingame, California, Quadric is building the world's first supercomputer designed for the real-time needs of edge devices. Quadric aims to empower developers in every industry with superpowers to create tomorrow's technology, today. The company was co-founded by technologists from MIT and Carnegie Mellon, who were previously the technical co-founders of the Bitcoin computing company 21. This is a rare opportunity to get in on the ground floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will contribute to all stages of the processor design cycle. Our preference is for a candidate located in the California Bay Area who can regularly collaborate from our Burlingame office. From time to time, the team and company gather for onsite meetings and offsite events. These in-person moments are an important part of how we build relationships, collaborate effectively, and align on priorities, and participation is expected for all team members.
Requirements
- BS/MS or Ph.D. in Electrical or Computer Engineering with a minimum of five years of CPU/GPU/ASIC front-end design
- Proficiency in SystemC, SystemVerilog, or Verilog
- Strong background in computer architecture
- Knowledge of design techniques for low power digital design
- Knowledge of VCS & Verilog/C Co-Sim
- Experience in data-parallel hardware design for high-performance computing
- Experience in logic synthesis and performance modeling
Nice To Haves
- Experience marketing semiconductor IP, AI accelerators, SoCs, EDA tools, or developer platforms.
- Familiarity with automotive safety (ASIL) standards
- Experience in FPGA design is a plus
Responsibilities
- Contribute to the definition of the processor architecture by understanding its applications
- Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog
- Own Power, Performance & Area (PPA) optimization
- Contribute to timing closure through full product cycle (front end, back-end, tapeout)
Benefits
- Medical, dental, and vision insurance from day one - Premiums covered at 99% for Employees
- Company-paid life Insurance
- Voluntary supplemental life insurance
- STD + LTD insurance
- Commuter support including parking or Caltrain reimbursement. Our office is conveniently located within walking distance of the Caltrain station
- FSA + HSA
- Equity with the business
- Paid Parental Leave
- 401(k) Retirement Plan
- Flexible PTO
- Winter holiday shutdown
- Catered lunch each day in our office
- Collaborative, low-ego culture with significant ownership and impact
- A work culture focused on innovative disruption
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What This Job Offers
Job Type
Full-time
Career Level
Senior
Education Level
Ph.D. or professional degree
