Senior FPGA & Firmware Engineer - SDR

Axon•Boston, MA

18d•$141,000 - $225,600•Hybrid

About The Position

As a senior member of Axon’s Mesh & Opportunistic Networking team, the engineer owns the FPGA implementation of digital signal processing for software-defined radio. The role takes wireless communication algorithms from concept and MATLAB/Simulink behavioral models through synthesizable RTL and silicon, meeting timing, resource, and power targets on a Zynq UltraScale+ MPSoC. The engineer applies expertise in DSP, digital communications, and FPGA design to deliver a high-performance OFDM modem, working closely with firmware, systems, RF, and product engineering to integrate the radio. The role also includes mentoring junior engineers and advancing model-based design and verification practices. The role is based in Axon’s Boston or Scottsdale offices and follows a hybrid schedule: onsite Tuesday through Friday, with remote work on Mondays, unless an approved workplace accommodation applies. The team emphasizes in-person collaboration, mentorship, and shared success. The position supports technology for law enforcement, public safety, and surrounding communities.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a similar engineering discipline.
At least 6 years of industry FPGA/RTL design experience taking digital logic from architecture through synthesis, timing closure, and hardware bring-up.
Highly proficient in RTL design with VHDL and/or Verilog/SystemVerilog, including synthesizable coding practices and design for testability.
Strong hands-on proficiency with the Xilinx/AMD Vivado toolchain, including synthesis, implementation, XDC timing constraints, and timing closure on complex, high-utilization designs.
Demonstrated experience with MATLAB and Simulink for algorithm modeling and model-based design workflows.
Solid foundation in digital signal processing and digital communications, including sampling, filtering, FFTs, modulation/demodulation, and wireless link fundamentals.
Experience with fixed-point arithmetic, quantization analysis, and trade-offs among numerical precision, area, and performance.
Proficiency with on-chip interconnect and interfaces, including AXI4/AXI4-Stream, DMA, memory interfaces, and clock-domain-crossing design.
Strong RTL verification skills, including testbench development, HDL simulation, and verification against a golden/reference model.
Hands-on proficiency in FPGA and system bring-up and debug with laboratory tools, including oscilloscopes, logic/protocol analyzers, spectrum/signal analyzers, and integrated logic analyzers (ILA/VIO).
Proficiency with modern AI-assisted development tools and coding assistants such as Claude Code, Cursor, and GitHub Copilot, and ability to use them effectively and responsibly for design, verification, scripting, documentation, and debug.
Ability to independently develop complex designs within cross-functional and geographically diverse engineering teams.
Strong proficiency with documentation, analysis, and presentation tools, including Word, Excel, and PowerPoint.

Nice To Haves

Master’s or PhD in Electrical Engineering, Communications, or Signal Processing.
Production experience with HDL Coder or equivalent high-level synthesis/model-to-RTL workflows, including code generation, optimization, and generated-RTL verification.
Hands-on experience implementing OFDM modems and/or channel coding such as LDPC, Turbo, or convolutional/Viterbi, as well as MIMO, channel estimation, and synchronization in hardware.
Experience designing on Zynq/Zynq UltraScale+ MPSoC or other heterogeneous SoC/FPGA platforms, including hardware/software partitioning with embedded processors.
Experience integrating wideband RF transceivers such as Analog Devices ADRV9001/ADRV9002 or other SDR front ends, and implementing or supporting RF impairment correction such as digital pre-distortion.
Familiarity with software-defined radio platforms and frameworks such as GNU Radio and over-the-air testing.
Experience with Git version control and CI for HDL/model-based design.
Experience applying AI coding assistants to FPGA/HDL workflows, including RTL generation and review, testbench creation, constraint and timing analysis, MATLAB/Simulink and Tcl scripting, and design documentation, with sound judgment about where generated output needs verification.

Responsibilities

Research, model, and implement SDR and digital communications algorithms, including OFDM modulation and demodulation, FFT/IFFT, channel estimation and equalization, synchronization, MIMO, and forward error correction such as LDPC.
Develop floating- and fixed-point behavioral reference models in MATLAB/Simulink; assess quantization and architecture trade-offs; and validate algorithm performance against link-budget and BER/PER requirements.
Generate and integrate RTL from Simulink using HDL Coder and author hand-written VHDL/Verilog for custom or performance-critical logic.
Implement designs in Vivado through synthesis, place-and-route, and timing closure, and author and refine XDC timing and physical constraints for high-utilization, multi-clock designs.
Architect and implement on-chip interfaces and data movement, including AXI4/AXI4-Stream, DMA, register interfaces, FIFOs, and clock-domain-crossing logic.
Build and maintain verification using Simulink/HDL co-simulation, bit-true reference-model comparison, RTL testbenches, and automated regression suites.
Integrate the modem with RF transceiver front ends such as ADRV9001 and ARM application cores, and partition functionality across the heterogeneous SoC.
Collaborate with electrical engineering on FPGA/RF boundary concerns, including power and thermal budgets, test and characterization waveforms, and digital pre-distortion for power amplifier linearization.
Bring up, characterize, and debug radio hardware using oscilloscopes, logic/protocol analyzers, spectrum and vector signal analyzers, and on-chip debug tools such as ILA/VIO.
Collaborate with firmware engineering to define and debug hardware/software interfaces, register maps, and data pipelines.
Evaluate and document design outcomes, timing/resource reports, and verification results; present findings for design-team review and follow-up.
Optimize performance, area, and power through micro-architecture refinement, pipelining, and resource sharing, guided by simulation and hardware measurement.
Develop and maintain design documentation, interface control documents, and release artifacts for product integration.
Mentor junior engineers and contribute to team knowledge sharing and best practices in model-based design and FPGA development.