Senior Director, Chipset Systems and SoC Architecture

Google•Mountain View, CA

7d•$364,000 - $505,000•Remote

About The Position

As Senior Director of the Chipset and System-on-a-Chip (SoC) Architecture Team, you will in an executive leadership role responsible for exploring, owning, and executing the architecture for future Google Tensor SoCs and chipsets. You will lead a consolidated organization of full-time employees whose primary mandate is to explore, analyze, and make recommendations on architecture options and innovations for future SoCs and chipsets, including topics such as memory architecture and chiplets; identify and drive across a cross-functional organization new system level features for performance and power optimization of critical user journeys; and ensure all architectural innovations are driven to commercialization. In this role, you will hold decision-making autonomy over SoC and chipset architecture exploration, analysis, recommendations, and drive to commercialization. The role requires experts' ability to make high-level trade-offs to drive system level hardware and software innovation. You will directly impacts the competitiveness of Google's flagship devices (e.g. Pixel) by seeing technology trends and preparing Tensor architecture for the future critical user journeys, particularly Imaging, GenAI, and Gemini use cases. Additionally, you will ensure that future generations of silicon are optimized for performance, power, and cost, especially for first-party use cases, widening Google's lead on consumer GenAI and Gemini on-device performance while preventing costly silicon area inflation and unproductized hardware blocks. You will direct a geographically distributed, vertically integrated organization across Mountain View, Bangalore, and Taiwan. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

Requirements

Bachelor's degree in Electrical Engineering, Computer Science, or a related field, or equivalent practical experience.
20 years of experience in SoC system architecture and hardware/software co-design for battery powered devices, driving SoC architecture changes for battery-powered devices to achieve improvement in power or performance or cost.
15 years of experience in people management, including experience leading multiple functional groups or a silicon design/architecture organization.
Experience with the commercialization of architecture changes (i.e., SoC and related software), not just evaluation and recommendations.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Science, or a related field.
20 years of experience with silicon system architecture or custom silicon design on process nodes in foundries.
Experience analyzing high-stakes workloads (e.g., GenAI, imaging, computer vision, etc.) and defining hardware-software boundaries (e.g., firmware, OS drivers, kernel virtualization).
Excellent change-management and operational leadership skills, with experience driving systemic organizational change or merging large engineering teams across global sites.
Technical knowledge of high-performance coherent fabrics, memory subsystems, and core IPs (including CPU, GPU, TPU, camera, and system security blocks).

Responsibilities

Lead the multi-year silicon system architecture roadmap for future Tensor SoCs. Establish and enforce a "directed innovation" model where all hardware and IP innovations have explicit software sponsorship.
Lead and scale a multi-disciplinary, geographically distributed organization of full-time employees across three core pillars. Provide mentorship, professional development, and strategic management to a team of senior leaders.
Integrate merged organizations and establish clear operational boundaries with implementation and IP core teams. Collaborate closely to set strict system target boundaries (e.g., chassis, power, limits, and performance) without displacing execution-level block architects.
Serve as the lead technical and strategic liaison to Google Executive Leadership.