Senior DRAM Systems Architecture

Micron Technology • San Jose, CA

1d • $164,000 - $358,000

About The Position

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our memory solutions power AI, cloud, enterprise, mobile, and high-performance computing platforms around the world. The Memory Systems Architecture team explores complex technical challenges across the memory stack and turns them into practical product innovations, helping shape the future of memory technologies and industry standards. As a Technical Staff Member, you will provide systems-level architecture leadership for next-generation memory solutions. This role combines analytical modeling, architecture development, reliability strategy, and cross-functional influence to help define future products. You will work across engineering disciplines to evaluate tradeoffs, guide technical decisions, and develop differentiated solutions that deliver value to customers and platforms.

Requirements

• Master's degree or equivalent experience in Electrical Engineering, Computer Engineering, Computer Science, Applied Mathematics, Physics, or a related technical field.
• 8+ years of experience in memory systems, semiconductor architecture, computer architecture, or related technical areas.
• Strong knowledge of DRAM architecture, memory systems, or high-performance computing system architecture.
• Proven ability to develop architecture recommendations using quantitative analysis and engineering tradeoffs.
• Experience using AI-powered tools and methodologies, including Large Language Models, Agentic AI, Generative AI, or AI-enabled simulation environments.

Nice To Haves

• Experience working with DDR, LPDDR, HBM, CXL memory, MRDIMM/RDIMM, or emerging memory technologies.
• Experience with memory-system simulation or modeling tools such as Ramulator, Ramulator2, DRAMsim3, gem5, internal simulators, or equivalent platforms.
• Experience in queueing theory, stochastic modeling, performance modeling, reliability modeling, or mathematical optimization.
• Experience with RAS architecture, ECC, CRC, EDC, metadata, on-die ECC, rank-level protection, link protection, or system-wide robustness.
• Background in high-speed signaling, SI, clock distribution, packaging, module, PMIC, power, or thermal systems and experience participating in JEDEC or similar standards organizations.

Responsibilities

• Define architectures for DDR, LPDDR, HBM, CXL-attached memory, and emerging memory technologies.
• Develop analytical and simulation-based models to evaluate performance, reliability, power, thermal, and cost tradeoffs.
• Drive architecture requirements across DRAM, packaging, modules, controllers, platforms, and system software.
• Lead technical studies, roadmap development, and architecture recommendations supported by quantitative analysis.
• Influence cross-functional teams, mentor engineers, and contribute to patents, publications, and standards activities.

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Senior