Senior Director, Architecture Research Lab

Samsung Semiconductor•San Jose, CA

22h•Onsite

About The Position

This role involves leading cutting-edge research on next-generation AI system architectures. The position is responsible for the end-to-end co-design of AI workloads, system-level modeling, hardware platforms, and high-performance processors that utilize Samsung's advanced memory technologies to overcome capacity, bandwidth, and large-scale communication bottlenecks. The role requires daily onsite presence at our San Jose Headquarters, in alignment with our Flexible Work policy.

Requirements

Ph.D. in Computer Science, Electrical Engineering, or a related field.
10+ years in system-level architecture research or large-scale computing platform design, with a strong focus on AI workloads.
Performance modeling, event-driven simulation, and quantitative analysis of compute-memory-interconnect systems.
Deep knowledge of modern CPU/accelerator architectures (RISC-V, ARM, x86) and heterogeneous integration.
Proven ability to design rack-scale AI system architectures that address memory, bandwidth, and interconnect constraints.
Proficiency with transaction-level modeling (TLM) and event-driven simulation for compute-memory-network co-design.
Experience in large-scale design-space exploration and PPA (performance, power, area/cost) trade-off analysis.
Expertise in architecture and micro-architecture design of out-of-order CPUs.
Hands-on experience with simulation tools and programming languages such as Python and C++.
Excellent written and verbal communication; proven ability to deliver technical presentations to senior stakeholders.

Nice To Haves

Proven track record of publishing high-impact research papers.
Experience influencing product roadmaps through architectural recommendations.
Strong collaborative history with cross-functional teams (hardware, software, memory technology).

Responsibilities

Define system-level architectures that solve memory-capacity, bandwidth, and interconnect challenges for large AI workloads (e.g., large language models, recommendation systems).
Build and maintain analytical and event-driven simulation frameworks for compute-memory-network performance at rack scale.
Conduct design-space exploration and quantitative trade-off studies (performance, power, cost) to guide architecture decisions.
Partner with SAIT HQ teams to align modeling insights with real-world AI system implementations.
Architect high-performance, out-of-order RISC-V CPU cores that serve as host processors for AI computing systems.
Drive IPC-focused feature path-finding; lead micro-architecture research through performance-model simulation and workload analysis.
Produce detailed micro-architecture specifications and guide cache/memory hierarchy design for optimal AI workload execution.
Lead a multidisciplinary research team, set technical roadmaps, and ensure delivery of high-impact publications.
Present architectural insights and strategic recommendations to senior leadership and external partners.