Senior DFT Methodology Engineer

NVIDIA•Santa Clara, CA

1d•$168,000 - $310,500•Hybrid

About The Position

We are now looking for a Senior DFT Methodology Engineer! As a Senior DFT Methodology Engineer, you will architect and develop the test methodologies that make our next generation of silicon testable, debuggable, and secure from the very first bring-up. NVIDIA has crafted creative solutions for DFT architecture, verification, and post-silicon validation on some of the industry’s most complex semiconductor chips. This powerful technology changed modern computer graphics and parallel computing. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.

Requirements

BS/MS Electrical or Computer Engineering (or equivalent experience) in related domain with proven DFT experience
10+ years of hands-on experience in SoC architecture, RTL design, and verification.
Strong analytical skills, with experience using vendor tools to verify and validate test patterns and logic on highly complex, multi-million-gate designs.
Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development
Exceptional written and oral interpersonal skills with the curiosity to work on rare challenges

Nice To Haves

Knowledge of DFT security and hardware system security is a plus.
Strong programming and scripting skills in Perl, Python, or Tcl
Proven track record of successfully deploying advanced DFT methodologies in groundbreaking semiconductor technologies
Experience mentoring engineers and driving methodology adoption across multiple product generations
Strong problem-solving skills and a proactive approach to overcoming technical challenges

Responsibilities

Own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, I1149.1, I1500, I1687, 1838, memory BIST, memory dump and DFX security methodology.
Partner closely with timing, physical design, software, bring-up, and production teams to make the right trade-offs between cost and quality.
Help architect, develop and deploy DFT methodologies for our next generation products including RTL design, Verification, pattern generation, partnering with teams like timing, physical design, software, bringup, production.
Help mentor junior engineers on test designs and trade-offs including cost and quality.