Senior Design Verification Engineer

Altera•Hillsboro, OR

2d•$169,000 - $240,000•Onsite

About The Position

Altera is seeking a highly motivated Senior Design Verification Engineer to join our FPGA Silicon Engineering team. In this role, you will be responsible for planning, developing, and executing comprehensive verification strategies for complex FPGA intellectual property (IP), subsystems, and SoC-level designs. You will collaborate closely with architecture, design, firmware, emulation, and validation teams to ensure first-pass silicon success and deliver high-quality products to our customers. The ideal candidate possesses deep expertise in modern verification methodologies, strong debugging skills, and a passion for solving complex technical challenges. This position offers the opportunity to work on cutting-edge FPGA architectures and influence verification excellence across multiple product generations.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and 10+ years of experience in Design Verification, ASIC, FPGA, or SoC development; OR Master's degree and 8+ years of experience; OR PhD and 6+ years of experience.
10+ years of hands-on experience developing and executing verification plans for complex digital designs, IPs, subsystems, or SoCs.
10+ years of experience using SystemVerilog for verification and testbench development.
8+ years of experience developing and maintaining UVM-based verification environments for block-level and/or system-level verification.
10+ years of experience applying constrained-random, assertion-based, and coverage-driven verification methodologies.
10+ years of experience debugging RTL and verification environment issues using industry-standard simulation and waveform debug tools.
5+ years of experience developing verification automation, infrastructure, or productivity tools using Python, Perl, Tcl, Shell, or similar scripting languages.
Demonstrated experience delivering verification closure on at least two full ASIC, FPGA, or SoC product development cycles from architecture through tapeout.
Experience analyzing and driving closure of functional and code coverage metrics across complex verification environments.
Proven ability to work effectively in cross-functional teams consisting of design, architecture, firmware, emulation, and validation engineers.

Nice To Haves

Experience verifying FPGA architecture components, programmable fabric, interconnects, memory subsystems, or high-speed interfaces.
Knowledge of industry-standard protocols such as PCIe, Ethernet, CXL, DDR, LPDDR, HBM, AXI, or AMBA.
Experience with formal verification tools and methodologies.
Experience with emulation platforms, FPGA prototyping, or hardware-assisted verification.
Familiarity with low-power verification methodologies.
Prior experience leading verification efforts for complex IPs or SoCs.
Experience working in a silicon product development environment from architecture through production.

Responsibilities

Define and execute verification plans for complex FPGA IPs, subsystems, and SoC components.
Develop scalable SystemVerilog/UVM-based verification environments and reusable verification infrastructure.
Create constrained-random, directed, and coverage-driven test strategies to validate design functionality.
Develop assertions, checkers, scoreboards, and protocol monitors to improve verification quality and efficiency.
Drive verification closure through functional, code, assertion, and toggle coverage analysis.
Perform RTL debugging and root-cause analysis of functional failures.
Collaborate closely with design, architecture, firmware, and validation teams to resolve issues throughout the development lifecycle.
Support emulation, FPGA prototyping, and post-silicon debugging activities when required.
Participate in design reviews and contribute to verification methodology improvements and best practices.
Mentor junior engineers and provide technical leadership within the verification team.