Senior ATE Test Engineer

Astera Labs•San Jose, CA

47d

About The Position

Astera Labs is seeking a Senior ATE Test Engineer with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define and implement ATE programs, and own the product from design, initial samples through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc. This role offers an opportunity to contribute hands-on technical expertise within Astera Labs’ hyper-growth connectivity business and help deliver purpose-built solutions that scale with the demands of rack-scale AI systems.

Requirements

Bachelor's in Electrical Engineering (Master's preferred).
At least 2 years of experience releasing complex SoC/silicon products to high volume manufacturing.
Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
Professional attitude with ability to execute on multiple tasks with minimal supervision.
Strong team player with good communication skills.
Entrepreneurial, open-mind behavior and can-do attitude.
Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.
Familiar with high-speed load board design techniques.
Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.
Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc.
Expertise in production test of high speed SerDes operating at 16Gbps and higher.
Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.
Experience with lab equipment including protocol analyzers and oscilloscopes.
Experience with using Advantest 93k ATE platform.
Proficiency in at least one modern programming language such as C/C++, Python.

Nice To Haves

Master's degree in Electrical Engineering.
Fluent in data processing using high level programming languages.
Experience in running External loopback at wafer sort.
Familiarity with modern databases.

Responsibilities

Develop and oversee SoC test strategy.
Interact with manufacturing partners.
Define and implement ATE programs.
Own the product from design, initial samples through high volume production ramp.
Collaborate with the design team to define test strategy, create and own the test plan.
Tester platform selection, design, and development of ATE hardware for wafer sort and final test.
Implement ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.
Develop DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.
Perform silicon/ATE bring-up, bench-ATE correlation and debug.
Run External loopback at wafer sort.