Staff ATE Test Engineer

Google•Sunnyvale, CA

2h•$192,000 - $278,000

About The Position

The Staff ATE Test Engineer will help develop custom silicon solutions for Google TPU technology powering AI/ML applications and data centers. The role serves as a technical leader in building SoCs for data centers, defining strategy and architecture for comprehensive Automatic Test Equipment (ATE) solutions in high-volume manufacturing. The engineer owns the end-to-end silicon test lifecycle and establishes methodologies connecting field performance, design, and testing for future chip generations. The role leads cross-functional efforts to integrate advanced SoC technologies into devices and architect robust manufacturing tests to ensure performance and yield. As a Staff Engineer, the person sets technical direction for test coverage and quality standards across the organization. The position is part of Google's AI and Infrastructure team, which delivers AI and infrastructure capabilities at scale, efficiency, reliability, and velocity.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in test engineering, product engineering, or silicon quality/reliability.
Experience in ASIC or SoC test development, bring-up, or debug.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
Experience with scan/ATPG test development or memory BIST test development and repair implementation.
Experience testing IPs such as PLLs, PVT sensors, temperature sensors, PMRO, and eFuse.
Experience with ATE probe card design and load board design.
Experience with UCIE, HBM, PCIE, and DDR.
Extensive experience with ATE from Advantest and Teradyne, such as EXA scale and UltraFlex+.

Responsibilities

Lead development and architectural definition of silicon test requirements, aligning strategies across design teams, DFT engineers, and external vendors.
Define and direct strategies for SoC product NPI, bring-up, verification, characterization, and qualification; resolve complex issues involving bench testing, test-coverage optimization, and system-to-ATE correlation.
Serve as an ATE testing domain expert, establish technical standards, architect scalable test solutions, and mentor engineering teams to drive systemic quality improvements.
Partner strategically with design, DFT, and quality teams to shape next-generation chip architectures, promote design-for-testability, and establish best practices for post-silicon testing.
Oversee and optimize the chip production lifecycle through improvements to test program architecture, volume data analytics, test time, yield, and RMA failure analysis.