Principal Engineer, ATE Test Development Engineer
Marvell Technology•Santa Clara, CA
•$136,880 - $205,000
About The Position
The Principal Test Engineer role offers Technical Leadership in Architecture and Scalability of Automated Test Equipment (ATE) test solutions for Hyperscale devices. This position outlines the Hyperscale Test Strategy, facilitates Cross-Functional Alignment, and oversees the development of ATE Test Programs that ensure robust Qualification, Comprehensive Test Coverage, and efficient High-Volume Manufacturing. As the primary Technical Authority, the role guarantees that Test Methodologies, Infrastructure, and execution adhere to the Performance, Quality, and Scalability Requirements outlined in the Product Roadmap.
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or any related discipline
- 5 to 10 years of experience in Semiconductor Test Engineering, with Demonstrated Technical Leadership on Complex SoC/ASIC/analog Test Programs
- Strong Hands-on Experience with Advantest 93000 ATE Platforms and SmarTest-8 Test Program Development
- Deep understanding of DFT techniques: scan, BIST, boundary scan/JTAG, ATPG, SSN, and Test Coverage Analysis
- Experience with Spanning New Product Introduction (NPI), Silicon Bring-up, Characterization, Correlation, and High‑Volume Manufacturing
- Proven Technical Leadership in High‑Speed and High‑Power Semiconductor Test Development for AI, Networking, and Advanced Hyperscale Products
- Deep expertise in ATE Test Methodologies, Silicon Process Fundamentals, DFT (Design-for-Test), DFM (Design-for-Manufacturing), High‑Speed SerDes, and High‑Power ATE testing.
- Track record of Building Scalable and Reusable ATE Test Libraries and Test Methods for MCM, CPC, and CPO Product Lines
- Proficiency in Scripting Test Automation, Data Analysis, and Computer Languages like Java, C/C++, Perl, and Python
- Excellent Cross-Functional Communication Skills, with experience Presenting Yield/Quality Data to Senior Leadership and Customers
- Demonstrates Strong Cross-Functional Communication Skills, with experience in Presenting Yield and Quality Data to Senior Leadership and Customers
- Possesses effective Communication Abilities, Strong teamwork, and Problem Solving Skills
- Self-motivated, Adaptable, and Capable of Thriving in Fast-Paced, Dynamic Engineering Environments
Responsibilities
- Define and own the End-to-End Test Strategy across Wafer Sort, Final Test, Production, and Wafer Sort on the Advantest 93K platform and System-Level Test (SLT) for new Silicon Test Programs
- Lead the Development of ATE Test Solutions, Silicon Bring-up and Characterization on new Tape-Outs, including Bench Validation, Correlation to simulation, Debug of First-Silicon Issues, Driving Cutting‑Edge Test Capability and ensuring Products meet the Highest Quality Standards
- Design and Develop High‑Speed ATE Hardware Supporting Data Rates above 112 Gbps, Advancing Next‑Generation Test Methodologies and enabling Future‑Ready Semiconductor Products
- Create Comprehensive Test Plans and Methodologies aligned with Stringent Product Specifications, ensuring Robust Validation and Consistent Product Performance
- Collaborate closely with DFT, DFM and Design teams to Review Testability and Test Strategies, Contributing to Improved Yield, Optimized Test Methodologies, and Cross‑Functional Innovation
- Convert Design‑level Test Content into ATE‑Ready Test Patterns, ensuring Seamless Transition from Simulation to Production Environments
- Drive Test Flow Optimization, Reducing Test Time, Eliminating Redundant Steps, Improving Yields, and Releasing High‑Quality Production Test Programs in Partnership with Cross‑Functional Engineering Teams
- Manage Cost-of-Test Initiatives across the Product Lifecycle
- Partner with Product Engineering, OSAT/foundry Test Floors on Test Program Transfer, Correlation, and Production Ramp Support
- Represent Test Engineering in Design Reviews, Providing Testability, Test Coverage, and Cost-of-Test input early in the Design Cycle
- Support Customer-Returns Technical Engagements (RMA), including Debug of Customer-Reported Silicon Issues and Test Escape Investigations
Benefits
- employee stock purchase plan with a 2-year look back
- family support programs
- robust mental health resources
- recognition and service awards
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What This Job Offers
Job Type
Full-time
Career Level
Principal
