Senior ASIC Silicon Validation Engineer (NetSec)

Palo Alto Networks • Office - USA - CA - Headquarters, CA

1d • $156,400 - $253,000 • Onsite

About The Position

As a Silicon Validation Engineer on the ASIC team, you will ensure that ASICs in next-generation firewall products meet or exceed requirements for features, performance, and reliability. You will define silicon validation methodologies, develop infrastructure, write and execute test plans, and debug issues. The role validates networking ASIC functionality for packet processing, switching, routing, cryptography, and high-speed interfaces.

Requirements

• BS or MS in EE, CE, or CS, or equivalent experience.
• At least 5 years of relevant silicon validation experience.
• Proven success taking ASICs to mass production.
• Proficiency with lab equipment, logic analyzers, and oscilloscopes.
• Background validating one or more high-speed interfaces: Ethernet, PCIE, DDR, or HBM.
• Expertise in Python and C.
• Demonstrated proficiency or active experience integrating modern AI tools into design, scripting, or validation workflows.
• Familiarity with SystemVerilog and ASIC verification tools such as VCS and Verdi.
• Demonstrated ownership and independence in planning, analyzing, debugging, driving vendors, and reporting status.
• Strong leadership, collaboration, and communication skills.

Nice To Haves

• Experience with networking and cybersecurity.

Responsibilities

• Create comprehensive silicon validation plans in collaboration with ASIC, system hardware, and software engineers.
• Develop silicon validation methodologies and infrastructure using lab equipment, third-party applications, and proprietary software-driven platforms.
• Execute all aspects of silicon validation test plans.
• Debug cross-functional issues with ASIC, system hardware, and software engineers to validate ASIC correctness.
• Build programs in Python and C to automate testing, regression, and debugging.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior