Senior ASIC Floorplan Design Engineer
About The Position
NVIDIA is seeking an experienced ASIC Floorplan Engineer to design and implement advanced SOCs, CPUs, and GPUs. The role contributes to the design and development of next-generation GPUs and SoCs from early architecture development through physical design, with products spanning consumer graphics, autonomous vehicles, and artificial intelligence. The engineer will partner with multidisciplinary teams from early chip definition to create floorplans that balance cost and area, performance, and power for target markets. They will develop floorplans, identify and resolve design and product risks, and create AI workflows and productivity tools to improve chip-area optimization and execution speed.
Requirements
- MSEE/MSCE or equivalent experience, with broad and deep experience in chip development.
- 10+ years of experience.
- Experience developing SOC, CPU, graphics, memory, and I/O subsystems in a chip.
- Ability to manage simultaneous projects and drive resolution of complex technical issues across multidisciplinary engineering teams.
- Experience with physical design methodologies, including flow and tools development, chip floorplanning, power/clock/reset distribution, DFT, place and route, timing closure, and packaging.
- Strong written, verbal, and technical communication skills to present progress and options and build alignment across multidisciplinary teams.
- Experience with agentic AI workflows and programming in Python, Perl, and/or C++.
Nice To Haves
- Experience driving development of large-scale ASIC floorplans for chiplet-based SOC and/or CPU projects.
- Strong algorithm development and programming skills.
- Ability to work effectively with incomplete data, evolving requirements, and tight schedules.
Responsibilities
- Partner with product managers, chip architects, ASIC design, physical design, packaging, and other teams from early chip definition to develop chip floorplans optimized for cost/area, performance, and power.
- Drive floorplan development and collaborate with ASIC and physical design teams to identify and address area, interconnect, timing, and floorplan improvement opportunities.
- Develop AI workflows and productivity tools to improve infrastructure for chip-area optimization and execution speed.
- Identify technical and product risks and work with engineering and management teams to develop risk-mitigation strategies.
Benefits
- Equity
- Benefits
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What This Job Offers
Job Type
Full-time
Career Level
Senior
