Senior ASIC Design Engineer

Cisco•San Jose, CA

5d•$167,700 - $245,200

About The Position

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Requirements

Bachelor’s degree in Electrical or Computer engineering and 7+ years of ASIC Design related experience, or Master’s degree in Electrical or Computer engineering and 4+ years of ASIC Design related experience, or PhD in Electrical or Computer engineering + 1 year of ASIC Design related experience
Experience with Verilog/System Verilog

Nice To Haves

At least one full ASIC tapeout (advanced nodes preferred).
Strong RTL skills with good command of timing closure, power, clock gating, and the full ASIC design flow.
Solid debug and scripting skills.
Good written and verbal communication skills.

Responsibilities

Author design specifications and participate in micro-architecture specification reviews.
Implement Verilog RTL to meet timing, performance, and power requirements
Develop and analyze functional coverage.
Collaborate with the verification team to address design corner cases and close coverage.
Work closely with physical design team to close design timing and place-and-route issues.
Perform diagnostic and post silicon validation tests in the lab.