Senior ASIC Design Engineer

Hewlett Packard Enterprise•Durham, NC

2d•$140,000 - $321,000•Hybrid

About The Position

This is a Hybrid role based in Durham, NC with an expectation that you’ll be in the office 2 days per week. US Citizenship Preferred. HPE Networking is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. At HPE Networking Silicon group, we push the boundaries of what is possible in a piece of silicon die. We build cutting edge networking chips used to build our world-class routers and switches. Bring your passion and there are no boundaries to what you can accomplish here. We are like a start-up in a big company. Year after year, our group builds the most powerful and highest density networking chips. As part of our fast-paced silicon group, you will become an expert in building high-speed ASICs, from specifications to final netlist. We give you opportunities to work on complex modules and subsystems where you can challenge yourself and grow. Open communications, empowerment, innovation, teamwork, and customer success are the foundations of team culture. Thus, you set your own limits for learning, achievements, and rewards. Position Summary We are seeking a highly motivated ASIC Design Engineer to join our networking silicon development team.

Requirements

Bachelor’s degree in Electrical or Computer Engineering required (Master’s strongly desired) with 7+ years of relevant experience.
Strong analytical/ problem solving skills.
Demonstrated skills in leading and implementing high performance modules from specification to final netlist.
Knowledge of Computer Architecture/networking protocols through prior work is strongly desired.

Responsibilities

Architect complex modules and subsystems used in high performance networking chips.
Write detailed functional as well as the micro-architecture specification for your module that meets power/area/performance targets.
Implement the design using Verilog or System Verilog
Write functional coverage/SVA to help verification catch corner case bugs.
Make sure your module meets the power targets by using state-of-the-art power reduction techniques during architecture and implementation phases.
Work with Physical design team for optimal floorplan and timing closure. Identify and fix timing in RTL to meet the frequency target.
Work with the Verification team to make sure your block is fully validated.
Provide guidance and mentoring to new college-grad engineers and interns.