Senior ASIC Design Verification Engineer (AI Compute)

Persimmons•San Jose, CA

21h•Onsite

About The Position

Persimmons is seeking a founding Senior ASIC Design Verification Engineer to own verification of its AI inference chiplet. The engineer will work closely with design, algorithm, compiler, and software teams to ensure the silicon meets its intended feature set and is free of critical bugs before tape-out. The role spans subsystem through full-chip verification, firmware testing, FPGA prototyping, and development of AI-driven verification workflows. The position is based on site in San Jose.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
At least 5 years of hands-on verification experience, including test-plan development, simulation environment creation, test implementation, and complex debugging across IP blocks, SoCs, and system-level designs.
Verification experience with compute and fabric datapaths.
Advanced SystemVerilog/Verilog and UVM skills.
C/C++ embedded code development and validation experience on RISC-V or similar processors.
Track record developing scalable verification flows and coverage-driven strategies, and using assertion-based and formal verification.
Ability to make data-driven decisions about what can be cut and what is non-negotiable before tape-out.
Experience building real AI-driven workflows, including writing agent instructions and shipping automation; regression triage, log analysis, or testbench generation experience is preferred.
Comfort leading and working hands-on in a small, high-ownership team, staying calm under pressure, and working on site in San Jose.

Nice To Haves

Experience building AI-driven automation for regression triage, log analysis, or testbench generation.

Responsibilities

Lead verification planning and execution from subsystem to full chip.
Collaborate with the CTO, design, and software teams to develop test plans that validate implementations against specifications.
Design and implement portable UVM testbenches with constrained-random stimulus, compute reference models, and scoreboards, supporting fast debugging.
Drive code, functional, and formal coverage closure, applying formal verification where it is most effective in compute logic.
Develop and validate C/C++ firmware tests running on RISC-V cores to exercise compute features end to end.
Extend verification through FPGA prototyping on Synopsys HAPS so software teams can run small real workloads.
Use AI agents to automate or improve testbench generation, stimulus creation, regression triage, log analysis, and coverage closure.
Run efficient automated regressions that conserve EDA licenses, analyze bug trends, and systematically drive bugs to closure.