Senior ASIC Design Verification Engineer (AI Compute)

Persimmons•San Jose, CA

1d•Onsite

About The Position

Persimmons is seeking a founding Senior ASIC Design Verification Engineer to own verification of its AI inference chiplet, which runs AI models of varying sizes. The engineer will work closely with design, algorithm, compiler, and software teams to ensure the silicon meets its intended feature set and is free of critical bugs before tape-out. The role is based on site in San Jose and involves hands-on work in a small, high-ownership team. The engineer will lead verification planning and execution from subsystem through full chip, create portable UVM testbenches and compute reference models, drive coverage closure, and apply formal verification where useful. The role also includes developing and validating C/C++ firmware tests on RISC-V cores, extending verification through Synopsys HAPS FPGA prototyping, applying AI agents to verification workflows, and running efficient automated regressions through bug closure.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
At least 5 years of hands-on verification experience spanning test plan development, simulation environment creation, test implementation, and complex debugging across IP blocks, SoCs, and system-level designs.
Verification experience on compute and fabric datapaths.
Advanced SystemVerilog/Verilog and UVM skills.
C/C++ embedded code development and validation experience on RISC-V or similar processors.
Track record of scalable verification flows, coverage-driven strategies, assertion-based verification, and formal verification.
Ability to make data-driven decisions about what can be cut and what is non-negotiable before tape-out.
Experience building real AI-driven workflows and shipping automation, ideally for regression triage, log analysis, or testbench generation; experience goes beyond simply chatting with a model.
Comfort leading and working hands-on in a small, high-ownership team, staying calm under pressure, and working on site in San Jose.

Responsibilities

Lead verification planning and execution from subsystem to full chip, collaborating with the CTO and design and software teams to create test plans that validate implementation against specifications.
Design and implement portable UVM testbenches with constrained-random stimulus, compute reference models, and scoreboards for subsystem- and chip-level verification and efficient debugging.
Drive code, functional, and formal coverage closure, applying formal verification where it is most effective in compute logic.
Develop and validate C/C++ firmware tests running on RISC-V cores to exercise compute features end to end.
Extend verification with FPGA prototyping on Synopsys HAPS so software teams can run small real workloads.
Use AI agents for verification tasks such as testbench generation, stimulus creation, regression triage, log analysis, and coverage closure.
Run efficient automated regressions that conserve EDA licenses, analyze bug trends, and systematically drive bugs to closure.